Patents by Inventor Laura Pescini

Laura Pescini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8258028
    Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: September 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Danny Pak-Chum Shum, Laura Pescini, Ronald Kakoschke, Karl Robert Strenz, Martin Stiftinger
  • Publication number: 20100203703
    Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 12, 2010
    Inventors: Armin Tilke, Danny Pak-Chum Shum, Laura Pescini, Ronald Kakoschke, Karl Robert Strenz, Martin Stiftinger
  • Patent number: 7679130
    Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: March 16, 2010
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Danny Pak-Chum Shum, Laura Pescini, Ronald Kakoschke, Karl Robert Strenz, Martin Stiftinger
  • Patent number: 7618492
    Abstract: Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: November 17, 2009
    Assignee: Infineon Technologies AG
    Inventors: Laura Pescini, Achim Gratz, Veronika Polei
  • Publication number: 20070034142
    Abstract: Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.
    Type: Application
    Filed: August 9, 2005
    Publication date: February 15, 2007
    Inventors: Laura Pescini, Achim Gratz, Veronika Polei
  • Publication number: 20060267134
    Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
    Type: Application
    Filed: March 3, 2006
    Publication date: November 30, 2006
    Inventors: Armin Tilke, Danny Shum, Laura Pescini, Ronald Kakoschke, Karl Strenz, Martin Stiftinger