Patents by Inventor Laura Pressley

Laura Pressley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230335425
    Abstract: Methods and systems allow a user or operator to easily create cyber-training environments for use in a cyber-training system. In one embodiment, the environments are configured as missions. The missions may have a plurality of features, such as training objectives, a mission storyline, a mission order and mission objectives, relative to a mission environment. The mission environment comprises a virtual environment, such as defined by a virtual network having virtual machines or devices.
    Type: Application
    Filed: March 2, 2023
    Publication date: October 19, 2023
    Inventors: Laura Lee, Raymond C. Prouty, Joseph T. Kowtko, Ryan Pressley
  • Patent number: 11666817
    Abstract: A mission-based cyber training platform allows both offensive and defensive oriented participants to test their skills in a game-based virtual environment against a live or virtual opponent. The system builds realistic virtual environments to perform the training in an isolated and controlled setting. Dynamic configuration supports unique missions using a combination of real and/or virtual machines, software resources, tools, and network components. Game engine behaves in a manner that will vary if participant attempts to replay a scenario based upon alternate options available to the engine. Scoring and leader boards are used to identify skill gaps/strengths and measure performance for each training participant. A detailed assessment of a player's performance is provided at the end of the mission and is stored in a user profile/training record.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: June 6, 2023
    Assignee: Circadence Corporation
    Inventors: Gary D. Morton, Mark Mihelic, Michael Moniz, Paul R. Thornton, Ryan Pressley, Laura Lee
  • Patent number: 6943569
    Abstract: A method and system to locate and detect voids in films that are involved in critical dimension (CD) structures and non-critical dimension structures in semiconductor devices are presented. One or more test structures (resolution devices) are formed on a semiconductor wafer. A scanning electron microscope is operated in voltage contrast mode to obtain a digital representation of the test structure. The voltage contrast image of the test structure is then analyzed with a system which automates the location, identification, and categorization of voids in the test structure. Additionally, the method is more sensitive to electrical marginalities caused by voids than other wafer electrical testing methods. The method is suitable inline monitoring during a manufacturing process by utilizing the automation of void identification, location, and categorization as a process monitoring parameter.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: September 13, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Laura Pressley, David E. Brown, Travis Lewis, Edward E. Ehrichs, Paul R. Besser
  • Patent number: 6566886
    Abstract: Various methods of inspecting circuit structures are provided. In one aspect, a method of detecting structural defects in a circuit structure is provided. A natural frequency of the circuit structure is determined and the circuit structure is immersed in a liquid. A first plurality of sonic pulses is sent through the liquid. The first plurality of sonic pulses have a first frequency range selected to produce a plurality of collapsing bubbles proximate the circuit structure. The collapsing bubbles produce a second plurality of sonic pulses that have a second frequency range near or including the natural frequency of the circuit structure whereby the second plurality of sonic pulses causes the circuit structure to resonate. Thereafter, the circuit structure is inspected for structural damage. Early identification of crystalline defects is facilitated.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: May 20, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Terri A. Couteau, Michael J. Satterfield, Laura A. Pressley
  • Patent number: 6524869
    Abstract: Various methods and apparatus are provided for testing an ion implantation tool. In one aspect, a method of testing an ion implanter is provided that includes forming a mask with a preselected pattern on a substrate. An ion implant is performed on the mask with the ion implanter. Following the ion implant, a scan of the mask is performed to identify any defects thereon. Defects appearing on the mask following the implant are indicative of latent mechanisms at work within the implanter. Ion implanter induced defects may be economically analyzed.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: February 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael J. Satterfield, Laura A. Pressley, Terri A. Couteau, Daniel E. Sutton, Bryon K. Hance, David Hendrix
  • Publication number: 20020142594
    Abstract: Various methods of processing a circuit structure with a protective coating are provided. In one aspect, a method of processing a semiconductor substrate is provided that includes patterning a structure on the substrate and forming a protective coating on the patterned structure while leaving other surfaces on the substrate exposed. The exposed surfaces are cleaned by immersing the substrate in a liquid and subjecting the exposed surfaces to sonic pulses whereby the protective coating increases the strength of the patterned structure to reduce the potential for structural failure induced by the sonic pulses. The protective coating is then removed.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 3, 2002
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Terri A. Couteau, Michael J. Satterfield, Laura A. Pressley, Bruce Pickelsimer
  • Patent number: 5961791
    Abstract: A via 42 is formed in an ILD layer 40 of a semiconductor device 30, using an etch chemistry which is highly selective to an underlying transition metal oxy-nitride film 38. In one form, film 38 is a TiO.sub.x N.sub.y film which is graded in nitrogen and oxygen concentration, being nitrogen rich at the bottom and oxygen reach at the top of the film. One method for forming TiO.sub.x N.sub.y is to sputter deposit a titantium layer 34 onto the semiconductor device using a titanium target 52. Using the same target, a TiN layer 36 is deposited by flowing nitrogen into the deposition chamber. Consequently, a TiN layer 58 is deposited onto target 52. The TiN layer 58 is then sputtered off the target onto the semiconductor device until eventually pure titanium is again being sputtered onto the device. The resulting deposited film has a grade titanium concentration, which is then oxidized to form the graded TiO.sub.x N.sub.y film.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: October 5, 1999
    Assignee: Motorola, Inc.
    Inventors: Larry E. Frisa, Hak-Lay Chuang, Laura Pressley