Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including determining whether one or more memory access operations performed on a range of consecutive wordlines of a memory device satisfy one or more criteria. The operations further include, responsive to determining that the one or more memory access operations satisfy the one or more criteria, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines of the memory device.

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including maintaining a counter to track a number of memory access operations performed on a range of consecutive wordlines in a block of the memory device. The operations further include determining that the number of memory access operations performed on the range of consecutive wordlines satisfies a threshold criterion. The operations further include, responsive to the number of memory access operations performed on the range of consecutive wordlines satisfying the threshold criterion, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines in the block of the memory device.

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including maintaining a counter to track a number of memory access operations performed on a range of consecutive wordlines in a block of the memory device. The operations further include determining that the number of memory access operations performed on the range of consecutive wordlines satisfies a threshold criterion. The operations further include, responsive to the number of memory access operations performed on the range of consecutive wordlines satisfying the threshold criterion, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines in the block of the memory device.

Abstract: A data structure including two or more entries is maintained, where each entry corresponds to a range of consecutive wordlines in a block of a memory device. Each entry includes an operation counter to track a number of memory access operations performed on the range of consecutive wordlines in the block of the memory device. An indication of a memory access operation pertaining to the particular wordline is received. In response to the indication of the memory access operation pertaining to the particular wordline, a determination is made whether the particular wordline is within any range of consecutive wordlines that has a corresponding entry in the data structure. In response to the particular wordline being outside of any range of consecutive wordlines that has a corresponding entry in the data structure, a new entry for a new range of consecutive wordlines that includes the particular wordline is created.

Abstract: A data structure including two or more entries is maintained, where each entry corresponds to a range of consecutive wordlines in a block of a memory device. Each entry includes an operation counter to track a number of memory access operations performed on the range of consecutive wordlines in the block of the memory device. An indication of a memory access operation pertaining to the particular wordline is received. In response to the indication of the memory access operation pertaining to the particular wordline, a determination is made whether the particular wordline is within any range of consecutive wordlines that has a corresponding entry in the data structure. In response to the particular wordline being outside of any range of consecutive wordlines that has a corresponding entry in the data structure, a new entry for a new range of consecutive wordlines that includes the particular wordline is created.

Abstract: A CMOS voltage translator having a differential cell circuit portion connected between first and second supply voltage references, and including first and second transistor pairs connected together in series between the supply voltage references. A first divider of the first supply voltage reference for producing a first reduced supply voltage reference on a first internal circuit node, and a second divider of the first supply voltage reference for producing a second reduced supply voltage reference on a second internal circuit node is included, as well as a multiplexer circuit portion connected between the first and second reduced supply voltage references to supply first and second reference voltages to the differential cell circuit portion, respectively on third and fourth internal circuit nodes.

Abstract: An internal reference voltage generating circuit includes first and second MOS transistors connected in series with each other between first and second voltage references in a pull-up/pull-down configuration, and linked together at an output terminal of the generation circuit whereon a reference output voltage is presented. The generation circuit includes first and second feedback paths between the output node and the first and second transistors, respectively, to provide an output reference voltage value which lies within a range centering about an inversion value.

Abstract: A CMOS voltage translator having a differential cell circuit portion connected between first and second supply voltage references, and including first and second transistor pairs connected together in series between the supply voltage references. A first divider of the first supply voltage reference for producing a first reduced supply voltage reference on a first internal circuit node, and a second divider of the first supply voltage reference for producing a second reduced supply voltage reference on a second internal circuit node is included, as well as a multiplexer circuit portion connected between the first and second reduced supply voltage references to supply first and second reference voltages to the differential cell circuit portion, respectively on third and fourth internal circuit nodes.

Abstract: A device for reading a memory including precharging circuits for precharging the inputs of a differential amplifier to a precharging voltage. The precharging voltage may be at an intermediate voltage level between a precharging voltage level of the bit lines and the voltage level of the logic supply voltage. This provides for a very fast build-up, during a following evaluation phase, of the output of the amplifier in a state corresponding to that of the cell being read. An internal detection circuit may also be included to detect an end of the precharging to stop the precharging circuit and activate the read current generator for the evaluation phase.