Patents by Inventor Laurance Cooke

Laurance Cooke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabrication of semiconductor device
    Publication number: 20060033124
    Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 16, 2006
    Applicant: eASIC Corporation
    Inventors: Zvi Or-Bach, Laurance Cooke
  • Semiconductor device having borderless logic array and flexible I/O
    Patent number: 6953956
    Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: October 11, 2005
    Assignee: eASIC Corporation
    Inventors: Zvi Or-Bach, Laurance Cooke
  • Method for fabrication of semiconductor device
    Publication number: 20050167701
    Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.
    Type: Application
    Filed: April 4, 2005
    Publication date: August 4, 2005
    Applicant: eASIC Corporation
    Inventors: Zvi Or-Bach, Laurance Cooke
  • Method for fabrication of semiconductor device
    Publication number: 20040119098
    Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Applicant: eASIC Corporation
    Inventors: Zvi Or-Bach, Laurance Cooke
  • Customizable and programmable cell array
    Patent number: 6642744
    Abstract: This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: November 4, 2003
    Assignee: eASIC Corporation
    Inventors: Zvi Or-Bach, Ze'ev Wurman, Richard Zeman, Laurance Cooke
  • Customizable and programmable cell array
    Publication number: 20020043988
    Abstract: This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plurality of the multiplicity of inputs and at least a plurality of the multiplicity of outputs.
    Type: Application
    Filed: October 5, 2001
    Publication date: April 18, 2002
    Inventors: Zvi Or-Bach, Ze?apos;ev Wurman, Richard Zeman, Laurance Cooke
  • Customizable and programmable cell array
    Patent number: 6331790
    Abstract: This invention discloses a customizable and programmable integrated circuit device including at least first and second programmable logic cells, and at least two electrical conductive paths interconnecting the at least first and second programmable logic cells, at least a portion of which can be removed for customization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: December 18, 2001
    Assignee: eASIC Corporation
    Inventors: Zvi Or-Bach, Ze'ev Wurman, Richard Zeman, Laurance Cooke