Patents by Inventor Laureen H. Parker
Laureen H. Parker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9653164Abstract: A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently.Type: GrantFiled: March 13, 2015Date of Patent: May 16, 2017Assignee: NXP USA, INC.Inventors: Cheong Min Hong, Laureen H. Parker
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Publication number: 20160267979Abstract: A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently.Type: ApplicationFiled: March 13, 2015Publication date: September 15, 2016Inventors: CHEONG MIN HONG, LAUREEN H. PARKER
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Patent number: 7842573Abstract: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.Type: GrantFiled: March 4, 2009Date of Patent: November 30, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Craig T. Swift, Gowrishankar L. G. Chindalore, Laureen H. Parker
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Publication number: 20090170262Abstract: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.Type: ApplicationFiled: March 4, 2009Publication date: July 2, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Craig T. Swift, Gowrishankar L. Chindalore, Laureen H. Parker
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Patent number: 7518179Abstract: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.Type: GrantFiled: October 8, 2004Date of Patent: April 14, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Craig T. Swift, Gowrishankar L. Chindalore, Laureen H. Parker
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Patent number: 7342833Abstract: A method for programming a non-volatile memory (NVM) cell includes applying an increasing voltage to the current electrode that is used as a source during a read. The initial programming source voltage results in a relatively small number of electrons being injected into the storage layer. Because of the relatively low initial voltage level, the vertical field across the gate dielectric is reduced. The subsequent elevation of the source voltage does not raise the vertical field significantly due to the electrons in the storage layer establishing a field that reduces the vertical field. With less damage to the gate dielectric during programming, the endurance of the NVM cell is improved.Type: GrantFiled: August 23, 2005Date of Patent: March 11, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Craig A. Cavins, Martin L. Niset, Laureen H. Parker
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Patent number: 5707889Abstract: An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.Type: GrantFiled: May 13, 1996Date of Patent: January 13, 1998Assignee: Motorola Inc.Inventors: Ting Chen Hsu, Laureen H. Parker, David G. Kolar, Philip J. Tobin, Hsing-Huang Tseng, Lisa K. Garling, Vida Ilderem
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Patent number: 5580815Abstract: An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.Type: GrantFiled: February 22, 1994Date of Patent: December 3, 1996Assignee: Motorola Inc.Inventors: Ting C. Hsu, Laureen H. Parker, David G. Kolar, Philip J. Tobin, Hsing-Huang Tseng, Lisa K. Garling, Vida Ilderem