Abstract: This disclosure is related to integrating microdevices into a system substrate. In particular the microdevices are transferred from a donor substrate into a system backplane where the microdevices connection pads are adhered to a pads on the system substrate at a temperature that is below the melting point of the materials on the pads of the system substrate and microdevice pads. The present disclosure also relates to integrating vertical microdevices into a system substrate. The system substrate can have a backplane circuit as well. The integration covers the microdevices with dielectrics and couples the backplane through a VIA. The disclosure further relates to a method and structure of microdevice or optoelectronic devices that allows for misalignment adjustment. The microdevices comprise a stack of semiconductor layers that in configuration with electrodes, substrate, VIA's and size factors minimize misalignment.

Abstract: What is disclosed is structures and methods of integrating blocks of microdevices into the system backplane. Process is outlined for forming blocks of microdevices and forming of transfer templates to facilitate transfer of blocks of microdevices to the system backplane. Further, aspects deal with microdevices forming blocks from different wafers and substrates.

Abstract: This disclosure is related to integrating pixelated microdevices into a system substrate to develop a functional system such as display, sensors, and other optoelectronic devices. The process may involve having a structure of release layers in the housing and then using different decoupling mechanisms for release. The release layers are not limited to but can be a combination of chemical or optical or mechanical release layers.

Abstract: Devices and methods for patterning the vertical solid state devices are provided. In some examples, a method of fabricating micro devices comprising forming device layers on a substrate, forming a first masking layer on a top layer of the device layers, forming a second masking layer on the first masking layer; and etching the device layers using the first and second masking layers to pattern the device layers.