Patents by Inventor Lauren MATSUMOTO

Lauren MATSUMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144002
    Abstract: A system that includes a machine learning model that is configured to receive an input layout file that includes a portion of an integrated circuit layout that has a previously identified wafer hotspot, match the previously identified wafer hotspot to one of a plurality of categories of wafer hotspot types, and output a proposed layout modification associated with the matching category of wafer hotspot types.
    Type: Application
    Filed: July 19, 2023
    Publication date: May 2, 2024
    Applicant: SanDisk Technologies LLC
    Inventors: Chen-Che Huang, Lauren Matsumoto, Chunming Wang
  • Patent number: 9859363
    Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 2, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Kota Funayama, Chun-Ming Wang, Jixin Yu, Chenche Huang, Tong Zhang, Daxin Mao, Johann Alsmeier, Makoto Yoshida, Lauren Matsumoto
  • Publication number: 20170236896
    Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.
    Type: Application
    Filed: May 16, 2016
    Publication date: August 17, 2017
    Inventors: Zhenyu LU, Kota FUNAYAMA, Chun-Ming WANG, Jixin YU, Chenche HUANG, Tong ZHANG, Daxin MAO, Johann ALSMEIER, Makoto YOSHIDA, Lauren MATSUMOTO