Abstract: An adaptive bias circuit for switched capacitor applications that compensates for temperature and process variations by maintaining a constant settling time of CMOS operational amplifiers is introduced. To this end, the adaptive bias circuit allows a dynamic trade-off between the slew-rate and the gain bandwidth product which allows the output of the operational amplifier to settle within a certain predetermined precision. A first aspect of the invention includes a current source providing a same current to a pair of transistors having different effective current densities. A resistor is coupled between the pair of transistors while from one end of the resistor, a constant bias current is drawn. In this manner, a voltage difference develops across the resistor which effectively indicates the change in the transconductance of the pair of transistors with respect to temperature and process variations.

Abstract: In a pipelined radix 2 analog to digital converter, a method of analog residue formation uses an overflow reduction stage which takes an analog input and outputs a digital value of +2, 0, or -2 and an analog residue which is twice the analog input minus the digital output value times a reference voltage. A calibration technique allows a pipelined analog to digital converter using the overflow reduction stages to produce a corrected output requiring one addition per pipeline stage. The residue portion of the overflow reduction stage can be constructed using an operational amplifier, two capacitors, one of which has twice the capacitance of the other, and three on-off type switches. A radix 2 pipelined converter is constructed using a combination of standard 1-bit stages and overflow reduction stages. The analog residue is passed from stage to stage as an amplifier remainder as the digital codes are extracted in a pipelined analog to digital converter.

Abstract: An analog to digital converter stage that has a very short sampling phase settling time requirement is used in a multistage pipelined analog to digital converter with a novel clocking design. Each clock period has a sampling phase and a hold phase. According to a first aspect, the sampling phase of each clock cycle is much shorter than the hold phase. This takes advantage of the reduced sampling phase settling time requirement of the analog to digital converter stage according to the present invention, and also allows a relatively longer hold phase during each clock cycle. The analog to digital converter stage according to the present invention is implemented with an operational amplifier such that during the sampling phase, the operational amplifier does not have to settle in order for correct sampling to occur, whereas operational amplifier settling is required during the hold phase.

Abstract: A comparator produces a digital output based upon a differential input signal and hysteresis. To inject positive feedback, a second differential pair is added. This feedback pair is nominally identical to the input pair. If the comparator has recently sensed a positive input of sufficient magnitude to drive the comparator output high, switches are turned on coupling a positive hysteresis voltage to the inputs of the feedback differential pair. By coupling a fixed current differential from the second differential pair to the input differential pair, the effective switching threshold of the comparator is changed. A non-overlapping clock generator is formed so that the switches will not turn on simultaneously so as to short the hysteresis reference voltage source. The hysteresis voltage source can be centered at any voltage that does not exceed the common mode range of the input pair.