Abstract: Techniques and logic are presented for encrypting and decrypting applications and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual L1 cache memory or between a processor's instruction and execution unit and their respective L1 caches. The logic may include one or more linear feedback shift registers (LFSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used for test purposes.

Abstract: A solar antenna array may comprise an emitter that may convert visible light into black body infrared radiation, and an array of antennas that may capture and convert the black body radiation into electrical power. Methods for constructing the solar antenna array may include using thermal insulation, high-gain low-e glass, and gasses with minimal heat transfer. A black body infrared antenna array may augment the electrical power from a visible light antenna array by converting its waste heat into additional electrical power.

Abstract: A solar antenna array may comprise an array of randomly placed carbon nanotube antennas that may capture and convert sunlight into electrical power. Methods for constructing the solar antenna array may use a mold and self aligning processing steps to minimize cost. Designs may be optimized for capturing a broad spectrum of non-polarized light. Alternatively, the array may generate light, and when connected in to an array of independently controllable sections may operate as either a reflective or light transmitting display.

Abstract: A solar antenna array may comprise an array of carbon nanotube antennas that may capture and convert sunlight into electrical power. A method for constructing the solar antenna array from a glass top down to aluminum over a plastic bottom such that light passing through the glass top and/or reflected off the aluminum both may be captured by the antennas sandwiched between. Techniques for patterning the glass to further direct the light toward the antennas and techniques for continuous flow fabrication and testing are also described.

Abstract: Techniques and logic are presented for encrypting and decrypting applications and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual L1 cache memory or between a processor's instruction and execution unit and their respective L1 caches. The logic may include one or more linear feedback shift registers (LFSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used for test purposes.

Abstract: A method for constructing a solar rectenna array by growing carbon nanotube antennas between lines of metal, and subsequently applying a bias voltage on the carbon nanotube antennas to convert the diodes on the tips of the carbon nanotube antennas from metal oxide carbon diodes to geometric diodes. Techniques for preserving the converted diodes by adding additional oxide are also described.

Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.

Abstract: A solar antenna array may comprise an array of carbon nanotube antennas that may capture and convert sunlight into electrical power. A method for constructing the solar antenna array from a glass top down to aluminum over a plastic bottom such that light passing through the glass top and/or reflected off the aluminum both may be captured by the antennas sandwiched between. Techniques for patterning the glass to further direct the light toward the antennas and techniques for continuous flow fabrication and testing are also described.

Abstract: A solar antenna array may comprise an array of antennas that may capture and convert sunlight into electrical power. Methods for constructing the solar antenna array may initially use range of semiconductor processing steps to minimize development costs, and may subsequently use a combination of stamps and low cost materials to reduce manufacturing costs. Designs may be optimized for capturing a broad spectrum of visible light and non-polarized light. Continuous flow Fabrication and Testing is also described.

Abstract: A solar antenna array may comprise an array of carbon nanotube antennas that may capture and convert sunlight into electrical power. A method for constructing the solar antenna array from a glass top down to an aluminum covered plastic bottom such that light passing through the glass top and/or reflected off the aluminum bottom both may be captured by the antennas sandwiched between. Techniques for patterning the glass to further direct the light toward the antennas and techniques for continuous flow fabrication and testing are also described.

Abstract: A semi-reflective display and a method for fabricating and assembling a semi-reflective display are presented, where the display may be comprised of visible light rectifying antenna arrays tuned to four different colors, which when forward biased may use electric power to amplify reflected colored light, and when reversed biased may generate electric power by absorbing light. TFT-tunnel diode logic may be used to control each sub-pixel.

Abstract: A design of a non-transistor memory core with corresponding shift register control logic may be all comprised of tunnel diodes and capacitors, and a method for fabricating such memories and control logic may use a stencil and non-lithographic self-aligning semiconductor processing steps to minimize cost. Designs and fabrication processes for I/O pads connected to the memory core and control logic are also presented.

Abstract: A semi-reflective display and a method for fabricating and assembling a semi-reflective display are presented, where the display may be comprised of visible light rectifying antenna arrays tuned to four different colors, which when forward biased may use electric power to amplify reflected colored light, and when reversed biased may generate electric power by absorbing light. TFT-tunnel diode logic may be used to control each sub-pixel.

Abstract: A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-fop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.

Abstract: A multi-processor system for data processing may utilize a plurality of different types of neural network processors to perform, e.g., learning and pattern recognition. The system may also include a scheduler, which may select from the available units for executing the neural network computations, which units may include standard multi-processors, graphic processor units (GPUs), virtual machines, or neural network processing architectures with fixed or reconfigurable interconnects.

Abstract: A design of a non-transistor memory core with corresponding shift register control logic may be all comprised of tunnel diodes and capacitors, and a method for fabricating such memories and control logic may use a stencil and non-lithographic self-aligning semiconductor processing steps to minimize cost. Designs and fabrication processes for I/O pads connected to the memory core and control logic are also presented.

Abstract: Techniques and logic are presented for encrypting and decrypting applications and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual L1 cache memory or between a processor's instruction and execution unit and their respective L1 caches. The logic may include one or more linear feedback shift registers (LFSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used for test purposes.

Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.

Abstract: Techniques and logic are presented for encrypting and decrypting programs and related data within a multi-processor system to prevent tampering. The decryption and encryption may be performed either between a system bus and a processor's individual L1 cache memory or between a processor's instruction and execution unit and their respective L1 caches. The logic may include one or more linear feedback shift registers (LFSRs) that may be used for generation of unique sequential address related codes to perform the decryption of instructions and transformation logic that may be used for generation of equivalent offset address related codes to perform decryption and encryption of data. The logic may also be programmable and may be used for test purposes.