Patents by Inventor Laurence R. Simar

Laurence R. Simar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7039790
    Abstract: A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execute packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. A predetermined bit in each instruction marks whether the next instruction is executed in parallel with the current instruction. Instructions in an execute packet are dispatched to appropriate functional execution units based on instruction type. Upon a branch into an execute packet instructions at memory addresses before the branch location are not executed in parallel with instructions following the branch location.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 2, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Laurence R. Simar, Jr., Richard A. Brown
  • Publication number: 20040044874
    Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.
    Type: Application
    Filed: September 2, 2003
    Publication date: March 4, 2004
    Inventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
  • Patent number: 6625719
    Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: September 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
  • Publication number: 20030056081
    Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.
    Type: Application
    Filed: June 14, 2002
    Publication date: March 20, 2003
    Inventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
  • Patent number: 6411984
    Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: June 25, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
  • Patent number: 6374346
    Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs” 102)and an arithmetic logic unit (“ALU” 104), capable of performing arithmetic operations and Boolean operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: April 16, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Natarajan Seshan, Laurence R. Simar, Jr., Reid E. Tatge, Alan L. Davis
  • Patent number: 6182203
    Abstract: A microprocessor, comprising a first set of functional units capable of performing parallel data operations, a second set of functional units capable of performing parallel data operations, and a data interconnection path connecting the first and second functional units.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: January 30, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Laurence R. Simar, Jr., Richard H. Scales, Natarajan Seshan
  • Patent number: 6055628
    Abstract: A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. These units form an instruction execution pipeline that operates without interlocks so that nestable delayed branch instructions are provided. The control circuitry for the instruction execution pipeline is operable to begin processing a second branch instruction having a second target address on a pipeline phase immediately after beginning processing of a first branch instruction having a first target address.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: April 25, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Natarajan Seshan, Laurence R. Simar, Jr.
  • Patent number: 5841379
    Abstract: A method for compression of digital data in a computer having a processor and a memory, wherein a group of consecutive bits having the same binary value is represented by a result number corresponding to the number of the consecutive bits. The method involves the following steps. A block of digital data to be compressed is provided. A bit detect selection parameter determines a bit value to be counted for counting consecutive bits. The processor is instructed to count from a first end of the block of digital data toward a second end of the block of digital data the number of consecutive bits having the bit value determined by the bit detect selection parameter. The number of bits so counted is stored, and the bit detect selection parameter is toggled. The processor is then instructed to count from the last bit counted toward the second end of the block of digital data the number of bits having the bit value determined by the current bit detect selection parameter.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: November 24, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Natarajan Seshan, Laurence R. Simar, Jr.
  • Patent number: 5826101
    Abstract: A data processing device comprising comprising a memory having a plurality of addressable memory locations, a processor circuit, an input register operative to hold input data, an output register operative to hold output data, and a direct memory access (DMA) circuit operative to receive input data from the input register for storing the input data in a first memory location and to concurrently send output data from a second memory location to said output register. Other devices, systems and methods are also disclosed.
    Type: Grant
    Filed: August 19, 1993
    Date of Patent: October 20, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Michael D. Beck, Laurence R. Simar
  • Patent number: 5809309
    Abstract: A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an arithmetic logic unit connected to the memory, operative to perform an arithmetic operation on data received by the arithmetic unit. An instruction decode and control unit connected to the memory, having an instruction register operative to hold a program instruction, is operative to decode a program instruction providing control signals to control the operations of the data processing device and to initiate a interrupt sequence responsive to an instruction code having a interrupt instruction. A program sequencer circuit connected to the memory, having a program register operative to hold a program counter corresponding to a program address is operative to access the memory with the program register to obtain the program instruction corresponding to the program address.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: September 15, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Jerald G. Leach, Laurence R. Simar
  • Patent number: 5751991
    Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.
    Type: Grant
    Filed: April 10, 1995
    Date of Patent: May 12, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge
  • Patent number: 5594914
    Abstract: A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address.
    Type: Grant
    Filed: October 20, 1994
    Date of Patent: January 14, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph A. Coomes, Steve P. Marshall, Laurence R. Simar
  • Patent number: 5535348
    Abstract: A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: July 9, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Jerald G. Leach, Joseph A. Coomes, Steve P. Marshall, Laurence R. Simar
  • Patent number: 5511146
    Abstract: A set of three cellular automata--the E-Cell, the I-Cell, and the D-Node--can be used to design and assemble parallel processing networks for such applications as signal processing and artificial intelligence. The E-Cell (FIG. 1a) is an excitory cell. The I-Cell (FIG. 2a) is an inhibitory cell. The D-Node (FIG. 3) is a combination of E-Cells and I-Cells. The use of the cellular automata is illustrated in three exemplary applications: a lateral inhibition network (FIG. 5b), a tree-search network (FIG. 6b), and a graph-search network (FIG. 7e). In particular, the tree-search and graph-search networks are implemented using the same structure as the tree or graph.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: April 23, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Laurence R. Simar, Jr.
  • Patent number: 5410652
    Abstract: A data processing device for use with another data processing circuit sending data and requests for service thereto. The data processing device includes a processor circuit, a communication port connected to said processor circuit, having a data buffer including a plurality of registers comprising a first-in-first-out (FIFO) circuit and a plurality of external terminals, the communication port operative to communicate with the external terminals. Further included is a FIFO control unit, connected to the registers of the FIFO circuit, operative to provide FIFO control signals for data transfers between the communication port and the FIFO circuit. A port arbitration unit, connected to the FIFO control unit, has a port arbitration register and is operative to exchange port control signals for arbitrating port control between requests from the processor circuit and the external terminals. Other devices, systems and methods are also disclosed.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: April 25, 1995
    Assignee: Texas Instruments, Incorporated
    Inventors: Jerald G. Leach, Laurence R. Simar
  • Patent number: 5390304
    Abstract: A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address.
    Type: Grant
    Filed: September 28, 1990
    Date of Patent: February 14, 1995
    Assignee: Texas Instruments, Incorporated
    Inventors: Jerald G. Leach, Laurence R. Simar
  • Patent number: 5305446
    Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.
    Type: Grant
    Filed: September 28, 1990
    Date of Patent: April 19, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Jerald G. Leach, Laurence R. Simar, Alan L. Davis, Reid E. Tatge