Patents by Inventor Laurene Yip

Laurene Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8410604
    Abstract: A semiconductor device includes a semiconductor die and a plurality of lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes a plurality of metal layers and a plurality of dielectric layers. One of the metal layers includes a plurality of contact pads corresponding to the plurality of lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having a plurality of respective openings for the contact pad. A plurality of respective copper posts is disposed on the contact pads. The respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad. The semiconductor die is mounted on the substrate with connections between the plurality of lead-free solder bumps and the plurality of copper posts.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: April 2, 2013
    Assignee: Xilinx, Inc.
    Inventors: Laurene Yip, Leilei Zhang, Kumar Nagarajan
  • Publication number: 20120098130
    Abstract: A semiconductor device includes a semiconductor die and lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes metal layers and dielectric layers. One of the metal layers includes contact pads corresponding to lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having respective openings for the contact pad. Respective copper posts are disposed on the contact pads. The respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad. The semiconductor die is mounted on the substrate with connections between the lead-free solder bumps and the copper posts.
    Type: Application
    Filed: October 26, 2010
    Publication date: April 26, 2012
    Applicant: XILINX, INC.
    Inventors: Laurene Yip, Leilei Zhang, Kumar Nagarajan
  • Patent number: 7906857
    Abstract: A molded integrated circuit package is described. The molded integrated circuit package comprises a substrate having a plurality of contacts on a first surface; a die having a plurality of solder bumps on a first surface, the plurality of solder bumps being coupled to the plurality of contacts on the first surface of the substrate; an adhesive material positioned on a second surface of the die; a lid attached to the adhesive material; and an encapsulant positioned between the lid and the substrate. Methods of forming molded integrated circuit packages are also disclosed.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: March 15, 2011
    Assignee: Xilinx, Inc.
    Inventors: Lan H. Hoang, Raghunandan Chaware, Laurene Yip