Patents by Inventor Laurent Barreau

Laurent Barreau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230230906
    Abstract: The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.
    Type: Application
    Filed: January 13, 2023
    Publication date: July 20, 2023
    Applicant: STMICROELECTRONICS (TOURS) SAS
    Inventors: Nicolas MODE, Ludovic FALLOURD, Laurent BARREAU
  • Publication number: 20200258818
    Abstract: A vertical power component includes a semiconductor substrate, a first electrode in contact with a lower surface of the substrate, and a second electrode in contact with an upper surface of the substrate. The vertical component is mounted to a metal connection plate via a metal spacer. The metal spacer includes a lower surface soldered to the metal connection plate and an upper surface soldered to the first electrode of the vertical power component. The metal spacer is made of a same metal as the metal connection plate. A surface are of the metal spacer mounted to the first electrode is smaller than a surface area of the first electrode.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 13, 2020
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Samuel MENARD, Laurent BARREAU
  • Patent number: 8840686
    Abstract: A method for encapsulating a thin-film lithium-ion type battery, including the steps of: forming, on a substrate, an active stack having as a lower layer a cathode collector layer extending over a surface area larger than the surface area of the other layers; forming, over the structure, a passivation layer including through openings at locations intended to receive anode collector and cathode collector contacts; forming first and second separate portions of an under-bump metallization, the first portions being located on the walls and the bottom of the openings, the second portions covering the passivation layer; and forming an encapsulation layer over the entire structure.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: September 23, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Pierre Bouillon, Patrick Hauttecoeur, Benoit Riou, Laurent Barreau
  • Patent number: 8785297
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Publication number: 20130043586
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Application
    Filed: October 11, 2012
    Publication date: February 21, 2013
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Patent number: 8319339
    Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: November 27, 2012
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Christophe Serre, Laurent Barreau, Vincent Jarry, Patrick Hougron
  • Patent number: 8309403
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: November 13, 2012
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Publication number: 20120199315
    Abstract: Described is an anti-condensation method for an aircraft (13), wherein part of a stream of cold air is withdrawn, the part of a stream of cold air is heated, and the part of the stream of hot air is introduced into the crown (19) of the aircraft (13) through an air introduction duct (8). Also described is an anti-condensation device called “Air Dryer System”.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 9, 2012
    Applicant: LIEBHERR-AEROSPACE TOULOUSE SAS
    Inventors: Laurent BARREAU, Michel EGLEM, Philippe HERAUD
  • Publication number: 20110124157
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 26, 2011
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Publication number: 20110052979
    Abstract: A method for encapsulating a thin-film lithium-ion type battery, including the steps of: forming, on a substrate, an active stack having as a lower layer a cathode collector layer extending over a surface area larger than the surface area of the other layers; forming, over the structure, a passivation layer including through openings at locations intended to receive anode collector and cathode collector contacts; forming first and second separate portions of an under-bump metallization, the first portions being located on the walls and the bottom of the openings, the second portions covering the passivation layer; and forming an encapsulation layer over the entire structure.
    Type: Application
    Filed: August 20, 2010
    Publication date: March 3, 2011
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Pierre Bouillon, Patrick Hauttecoeur, Benoit Riou, Laurent Barreau
  • Publication number: 20110006423
    Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 13, 2011
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Christophe Serre, Laurent Barreau, Vincent Jarry, Patrick Hougron