Patents by Inventor Laurent Barreau
Laurent Barreau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230230906Abstract: The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.Type: ApplicationFiled: January 13, 2023Publication date: July 20, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventors: Nicolas MODE, Ludovic FALLOURD, Laurent BARREAU
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Publication number: 20200258818Abstract: A vertical power component includes a semiconductor substrate, a first electrode in contact with a lower surface of the substrate, and a second electrode in contact with an upper surface of the substrate. The vertical component is mounted to a metal connection plate via a metal spacer. The metal spacer includes a lower surface soldered to the metal connection plate and an upper surface soldered to the first electrode of the vertical power component. The metal spacer is made of a same metal as the metal connection plate. A surface are of the metal spacer mounted to the first electrode is smaller than a surface area of the first electrode.Type: ApplicationFiled: February 10, 2020Publication date: August 13, 2020Applicant: STMicroelectronics (Tours) SASInventors: Samuel MENARD, Laurent BARREAU
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Patent number: 8840686Abstract: A method for encapsulating a thin-film lithium-ion type battery, including the steps of: forming, on a substrate, an active stack having as a lower layer a cathode collector layer extending over a surface area larger than the surface area of the other layers; forming, over the structure, a passivation layer including through openings at locations intended to receive anode collector and cathode collector contacts; forming first and second separate portions of an under-bump metallization, the first portions being located on the walls and the bottom of the openings, the second portions covering the passivation layer; and forming an encapsulation layer over the entire structure.Type: GrantFiled: August 20, 2010Date of Patent: September 23, 2014Assignee: STMicroelectronics (Tours) SASInventors: Pierre Bouillon, Patrick Hauttecoeur, Benoit Riou, Laurent Barreau
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Patent number: 8785297Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.Type: GrantFiled: October 11, 2012Date of Patent: July 22, 2014Assignee: STMicroelectronics (Tours) SASInventors: Marc Feron, Vincent Jarry, Laurent Barreau
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Publication number: 20130043586Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.Type: ApplicationFiled: October 11, 2012Publication date: February 21, 2013Applicant: STMicroelectronics (Tours) SASInventors: Marc Feron, Vincent Jarry, Laurent Barreau
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Patent number: 8319339Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.Type: GrantFiled: July 8, 2010Date of Patent: November 27, 2012Assignee: STMicroelectronics (Tours) SASInventors: Christophe Serre, Laurent Barreau, Vincent Jarry, Patrick Hougron
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Patent number: 8309403Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.Type: GrantFiled: November 16, 2010Date of Patent: November 13, 2012Assignee: STMicroelectronics (Tours) SASInventors: Marc Feron, Vincent Jarry, Laurent Barreau
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Publication number: 20120199315Abstract: Described is an anti-condensation method for an aircraft (13), wherein part of a stream of cold air is withdrawn, the part of a stream of cold air is heated, and the part of the stream of hot air is introduced into the crown (19) of the aircraft (13) through an air introduction duct (8). Also described is an anti-condensation device called “Air Dryer System”.Type: ApplicationFiled: February 9, 2012Publication date: August 9, 2012Applicant: LIEBHERR-AEROSPACE TOULOUSE SASInventors: Laurent BARREAU, Michel EGLEM, Philippe HERAUD
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Publication number: 20110124157Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.Type: ApplicationFiled: November 16, 2010Publication date: May 26, 2011Applicant: STMicroelectronics (Tours) SASInventors: Marc Feron, Vincent Jarry, Laurent Barreau
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Publication number: 20110052979Abstract: A method for encapsulating a thin-film lithium-ion type battery, including the steps of: forming, on a substrate, an active stack having as a lower layer a cathode collector layer extending over a surface area larger than the surface area of the other layers; forming, over the structure, a passivation layer including through openings at locations intended to receive anode collector and cathode collector contacts; forming first and second separate portions of an under-bump metallization, the first portions being located on the walls and the bottom of the openings, the second portions covering the passivation layer; and forming an encapsulation layer over the entire structure.Type: ApplicationFiled: August 20, 2010Publication date: March 3, 2011Applicant: STMicroelectronics (Tours) SASInventors: Pierre Bouillon, Patrick Hauttecoeur, Benoit Riou, Laurent Barreau
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Publication number: 20110006423Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.Type: ApplicationFiled: July 8, 2010Publication date: January 13, 2011Applicant: STMicroelectronics (Tours) SASInventors: Christophe Serre, Laurent Barreau, Vincent Jarry, Patrick Hougron