Patents by Inventor Laurent Brunet

Laurent Brunet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497627
    Abstract: A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: December 3, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Laurent Brunet, Perrine Batude
  • Patent number: 10490451
    Abstract: A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Brunet, Nicolas Posseme
  • Publication number: 20190198397
    Abstract: Fabrication of a circuit with superposed transistors, comprising assembly of a structure comprising transistors formed from a first semiconducting layer with a support (100) provided with a second semiconducting layer (102) in which transistors are provided on a higher level (N2), the second semiconducting layer (102) being coated with a thin layer (101) of silicon oxide, the assembly of said structure and the support (100) being made by direct bonding in which the thin silicon oxide layer (101) is bonded to oxidised portions (37b, 37c) of getter material.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 27, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois ANDRIEU, Lamine Benaissa, Laurent Brunet
  • Patent number: 10319628
    Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 11, 2019
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Fabien Deprat, Perrine Batude, Laurent Brunet, Claire Fenouillet-Beranger, Maud Vinet
  • Publication number: 20180090366
    Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Fabien DEPRAT, Perrine BATUDE, Laurent BRUNET, Claire FENOUILLET-BERANGER, Maud VINET
  • Publication number: 20170372967
    Abstract: A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 28, 2017
    Inventors: Laurent BRUNET, Nicolas POSSEME
  • Patent number: 9779982
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine Batude, Laurent Brunet, Claire Fenouillet-Beranger, Frank Fournel
  • Publication number: 20170221767
    Abstract: A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 3, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Laurent BRUNET, Perrine BATUDE
  • Patent number: 9689913
    Abstract: A method for measuring the changes of the electrical performance of an FDSOI transistor between a first and a second state of the transistor after an operating period t1, including the following steps: measurement of the transistor's capacities C1 and C2 respectively in the first and second states, according to a voltage VFG applied between the gate and the source and drain areas, determination, in relation to characteristic C1(VFG) varying between a maximum value Cmax and a minimum value Cmin, with three inflection points, of an ordinate value Cplat of C1(VFG) at the second inflection point of C1(VFG), and of two abscissa values VUpper(0) and VLower(0) of C1(VFG) according to equations VUpper(0)=C1?1((Cmax+Cplat)/2) and VLower(0)=C1?1((Cmin+Cplat)/2), determination, from characteristic C2(VFG), of two abscissa values VUpper(t1) and VLower(t1) of C2(VFG) according to equations VUpper(t1)=C2?1((Cmax+Cplat)/2) and VLower(t1)=C2?1((Cmin+Cplat)/2), determination of variations of defect densities ?Dit1, ?Dit2 b
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: June 27, 2017
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Xavier Garros, Laurent Brunet
  • Publication number: 20170178950
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 22, 2017
    Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine BATUDE, Laurent BRUNET, Claire FENOUILLET-BERANGER, Frank FOURNEL
  • Patent number: 8896466
    Abstract: In one aspect of the method for displaying an image on a screen of a cockpit of an aircraft, control means: control a first display on the screen of an image comprising a background; and then control a second display so that, in at least one zone of the image that is determined independently of the background, the background presents a non-zero second mean luminance that is less than a first mean luminance that it presented during the first display. In another aspect, the control means control the display on the screen of an image comprising a background in such a manner, that at least in a zone of the image that is determined independently of the background, the background presents non-zero mean luminance that is less than mean luminance of the remainder of the background.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 25, 2014
    Assignees: Airbus Operations (S.A.S.), Airbus (S.A.S.)
    Inventors: Laurent Georges, Remi Cabaret De Alberti, Laetitia Lambinet, Laurent Brunet
  • Patent number: 8525528
    Abstract: A method for evaluating the electric performances of an FDSOI transistor, including the steps of: measuring capacitance and/or conductance of the FDSOI transistor, by applying a voltage VBG>0 on a substrate composed of semiconductor of the FDSOI transistor when the FDSOI transistor is NMOS or a voltage VBG<0 on the substrate composed of semiconductor of the FDSOI transistor when the FDSOI transistor is PMOS, depending on a voltage VFG applied between a gate and source and drain regions of the FDSOI transistor.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: September 3, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Xavier Garros, Laurent Brunet
  • Publication number: 20110050253
    Abstract: A method for evaluating the electric performances of an FDSOI transistor, including the steps of: measuring the capacitance and/or the conductance of the FDSOI transistor, by applying a rear voltage VBG>0 or VBG<0 on the substrate of the transistor, depending on a front voltage VFG applied on the gate of the transistor, calculating the theoretical values of the capacitance and/or the conductance of a transistor modeled by an electric circuit equivalent to the FDSOI transistor, for different selected theoretical values of defect densities Dit1, Dit2 at the dielectric-semiconductor interfaces of the modeled transistor, determining the real values of Dit1, Dit2 at the corresponding interfaces of the FDSOI transistor by a comparison between the measured values of the capacitance and/or the conductance of the FDSOI transistor and the calculated theoretical values of the capacitance and/or the conductance of the modeled transistor.
    Type: Application
    Filed: August 20, 2010
    Publication date: March 3, 2011
    Applicant: Comm. a l' ener. atom. et aux energies alter.
    Inventors: Xavier GARROS, Laurent BRUNET
  • Publication number: 20110018742
    Abstract: In one aspect of the method for displaying an image on a screen of a cockpit of an aircraft, control means: control a first display on the screen of an image comprising a background; and then control a second display so that, in at least one zone of the image that is determined independently of the background, the background presents a non-zero second mean luminance that is less than a first mean luminance that it presented during the first display. In another aspect, the control means control the display on the screen of an image comprising a background in such a manner, that at least in a zone of the image that is determined independently of the background, the background presents non-zero mean luminance that is less than mean luminance of the remainder of the background.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 27, 2011
    Applicants: AIRBUS OPERATIONS, AIRBUS
    Inventors: Laurent Georges, Remi Cabaret De Alberti, Laetitia Lambinet, Laurent Brunet