Patents by Inventor Laurent Chalard

Laurent Chalard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7600172
    Abstract: A device for decoding an incident FEC encoded packet of data within an ARQ scheme. The device includes a processor or processing means for performing successive decoding processes of successive intermediate FEC code encoded packets related to the incident FEC code encoded packet. The processor or processing means includes a FEC decoder. The processor or processing means included a determination unit or determination means for determining initial decoding conditions from the FEC code decoding result concerning the preceding intermediate FEC code encoded packet and from the current intermediate FEC code encoded packet, and the FEC decoder is for performing the current FEC code decoding using the initial decoding conditions.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: October 6, 2009
    Assignee: STMicroelectronics N.V.
    Inventors: Friedbert Berens, Laurent Chalard, Stèphane Erkan Tanrikulu, Ettore Messina
  • Patent number: 7493551
    Abstract: The method and device include determining by removing N?N, rows from an original generator matrix (G) defining the LDPC code and having N rows and N?M columns for obtaining a generator sub-matrix (G1) having N?M columns and N1 rows. The method also includes delivering by receiving an input data vector of size N?M and multiplying the input vector with the generator sub-matrix for obtaining the punctured encoded code word.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: February 17, 2009
    Assignee: STMicroelectronics N.V.
    Inventors: Friedbert Berens, Laurent Chalard
  • Publication number: 20060156163
    Abstract: A device for decoding an incident FEC encoded packet of data within an ARQ scheme. The device includes a processor or processing means for performing successive decoding processes of successive intermediate FEC code encoded packets related to the incident FEC code encoded packet. The processor or processing means includes a FEC decoder. The processor or processing means included a determination unit or determination means for determining initial decoding conditions from the FEC code decoding result concerning the preceding intermediate FEC code encoded packet and from the current intermediate FEC code encoded packet, and the FEC decoder is for performing the current FEC code decoding using the initial decoding conditions.
    Type: Application
    Filed: December 2, 2005
    Publication date: July 13, 2006
    Applicant: STMicroelectronics N.V.
    Inventors: Friedbert Berens, Laurent Chalard, Stephane Tanrikulu, Ettore Messina
  • Publication number: 20060064627
    Abstract: The method and device include determining by removing N?N, rows from an original generator matrix (G) defining the LDPC code and having N rows and N?M columns for obtaining a generator sub-matrix (G1) having N?M columns and N1 rows. The method also includes delivering by receiving an input data vector of size N?M and multiplying the input vector with the generator sub-matrix for obtaining the punctured encoded code word.
    Type: Application
    Filed: September 21, 2005
    Publication date: March 23, 2006
    Applicant: STMicroelectronics N.V.
    Inventors: Friedbert Berens, Laurent Chalard