Abstract: A system for firing a projectile mounted on a carrier, the decision assistance system comprising: a first simulator for simulating a navigation system of the carrier and configured to produce a precision of a solution for navigation of the carrier; a second simulator for simulating a navigation system of the projectile and configured to be initialized with the precision of the solution for navigation of the carrier and produce a precision of a solution for navigation of the projectile; and a selector configured to select or not the projectile as projectile to be fired as a function of the precision of a solution for navigation of the projectile.

Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

Abstract: A compression method includes simplifying a mesh that represents a textured 3D-object by replacing polygons in the mesh with new ones that have broader faces. The method includes identifying adjacent polygons with different textures and adding vertices at the same positions as two vertices in the polygons. This creates two new edges and an intermediate polygon interposed between the two adjacent polygons. The new edges have zero length and the new polygon has zero area.

Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

Abstract: A compression method includes simplifying a mesh that represents a textured 3D-object by replacing polygons in the mesh with new ones that have broader faces. The method includes identifying adjacent polygons with different textures and adding vertices at the same positions as two vertices in the polygons. This creates two new edges and an intermediate polygon interposed between the two adjacent polygons. The new edges have zero length and the new polygon has zero area.

Abstract: There is described a charge pump circuit (1) circuit comprising an input terminal, an output terminal (5) connected to an intermediate node (Ni), a ground terminal (4), a first fly capacitor module (21) with a first fly capacitor (Cfly1) having a first pin (211) and a second pin (212) and connected to the intermediate node (Ni); and a second fly capacitor module (22) with a first fly capacitor (Cfly2) having a first pin (221) and a second pin (222) and connected to the intermediate node (Ni); wherein each being adapted to successively charge and discharge a the first fly capacitor and the second fly capacitor, respectively, wherein the second pin (212) of the first fly capacitor module (21) is connected to the first pin (221) of the second fly capacitor module (22) by a direct connection.

Abstract: A multi level charge pump circuit may be associated with at least two power supplies, and may provide at least four levels of positive and negative voltage. The multi level charge pump may include first and second fly capacitors, and first and second tank capacitors. A plurality of PMOS transistors and NMOS transistors may allow generation of two high voltage levels and two low voltage levels for the multi level charge pump, the low voltage levels being derived from a charging of the two fly capacitors in series. This multi level charge pump may be embodied in an audio device within a platform without a dedicated SMPS circuit.

Abstract: A multi level charge pump circuit may be associated with at least two power supplies, and may provide at least four levels of positive and negative voltage. The multi level charge pump may include first and second fly capacitors, and first and second tank capacitors. A plurality of PMOS transistors and NMOS transistors may allow generation of two high voltage levels and two low voltage levels for the multi level charge pump, the low voltage levels being derived from a charging of the two fly capacitors in series. This multi level charge pump may be embodied in an audio device within a platform without a dedicated SMPS circuit.

Abstract: There is described a charge pump circuit (1) circuit comprising an input terminal, an output terminal (5) connected to an intermediate node (Ni), a ground terminal (4), a first fly capacitor module (21) with a first fly capacitor (Cfly1) having a first pin (211) and a second pin (212) and connected to the intermediate node (Ni); and a second fly capacitor module (22) with a first fly capacitor (Cfly2) having a first pin (221) and a second pin (222) and connected to the intermediate node (Ni); wherein each being adapted to successively charge and discharge a the first fly capacitor and the second fly capacitor, respectively, wherein the second pin (212) of the first fly capacitor module (21) is connected to the first pin (221) of the second fly capacitor module (22) by a direct connection.

Abstract: Each switching element of a charge pump circuit of a voltage regulator comprises a relatively small-sized MOS transistor associated with a relatively large-sized MOS transistor connected in parallel. Only the small transistors are switched in a first mode of operation, while the large transistors are switched in a second mode of operation. In this manner the switching losses in the first mode of operation can be decreased.

Abstract: The invention relates to a switching mode power supply device comprising at least one MOS power transistor made on an integrated circuit and operating in switching mode, the drain and the source of said at least one MOS power transistor being connected, via connecting members having a non-null inductance, to one or several external circuits to said integrated circuit. According to the invention, the device further comprises a limiter circuit able to limit the current variations in at least one of said connecting members during the switching of said MOS power transistor. This limiter circuit enables to maintain the drain-source voltage of the MOS power transistor below a predetermined threshold value when it commutes.

Abstract: A dual voltage charge pump circuit to be associated with one power supply for the purpose of generating two positive and negative output voltages, with two different low and high levels. The circuit comprises two flying capacitors and two tank capacitors. PMOS transistors and NMOS transistor for achieving the charge transfer between the fly capacitor and the respective tank capacitor. Additional transistors are used for providing a low voltage charge pump as well as charge compensation between the two fly capacitors. Preferably, one fly capacitor has one end directly connected to the ground, what reduces the complexity of the dual charge pump and achieves saving of MOS transistor and ball.

Abstract: A dual voltage charge pump circuit to be associated with one power supply for the purpose of generating two positive and negative output voltages, with two different low and high levels. The circuit comprises two flying capacitors and two tank capacitors. PMOS transistors and NMOS transistor for achieving the charge transfer between the fly capacitor and the respective tank capacitor. Additional transistors are used for providing a low voltage charge pump as well as charge compensation between the two fly capacitors. Preferably, one fly capacitor has one end directly connected to the ground, what reduces the complexity of the dual charge pump and achieves saving of MOS transistor and ball.

Abstract: The invention relates to a switching mode power supply device comprising at least one MOS power transistor made on an integrated circuit and operating in switching mode, the drain and the source of said at least one MOS power transistor being connected, via connecting members having a non-null inductance, to one or several external circuits to said integrated circuit. According to the invention, the device further comprises a limiter circuit able to limit the current variations in at least one of said connecting members during the switching of said MOS power transistor. This limiter circuit enables to maintain the drain-source voltage of the MOS power transistor below a predetermined threshold value when it commutes.