Patents by Inventor Laurent Dedieu

Laurent Dedieu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Secure non-volatile memory
    Patent number: 9406372
    Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 2, 2016
    Assignee: STMicroelectronics SA
    Inventors: Philippe Candelier, Laurent Dedieu, Noureddine Larhriq
  • Secure non-volatile memory
    Patent number: 8432726
    Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: April 30, 2013
    Assignee: STMicroelectronics SA
    Inventors: Philippe Candelier, Laurent Dedieu, Noureddine Larhriq
  • SECURE NON-VOLATILE MEMORY
    Publication number: 20120120716
    Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 17, 2012
    Applicant: STMICROELECTRONICS SA
    Inventors: Philippe Candelier, Laurent Dedieu, Noureddine Larhriq
  • Non-volatile memory device including bistable circuit with pre-load and set phases and related system and method
    Patent number: 7697319
    Abstract: An embodiment of a device for memorization of a memory bit is provided, comprising a bistable circuit having complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: April 13, 2010
    Assignee: STMicroelectronics, SA
    Inventors: Laurent Dedieu, Sebastien Lefebvre
  • Non-volatile memory device and related system and method
    Publication number: 20070211520
    Abstract: An embodiment of the invention relates to a device for memorisation of a memory bit, provided with a bistable circuit with complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.
    Type: Application
    Filed: February 14, 2007
    Publication date: September 13, 2007
    Inventors: Laurent Dedieu, Sebastien Lefebvre