Patents by Inventor Laurent Gay
Laurent Gay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11610933Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: GrantFiled: May 21, 2021Date of Patent: March 21, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
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Publication number: 20220336520Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Laurent GAY, Frederic LALANNE, Yann HENRION, Francois GUYADER, Pascal FONTENEAU, Aurelien SEIGNARD
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Patent number: 11398521Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.Type: GrantFiled: January 10, 2020Date of Patent: July 26, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
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Publication number: 20210288102Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: ApplicationFiled: May 21, 2021Publication date: September 16, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Frederic LALANNE, Laurent GAY, Pascal FONTENEAU, Yann HENRION, Francois GUYADER
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Patent number: 11031433Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: GrantFiled: February 8, 2019Date of Patent: June 8, 2021Assignee: STMicroelectronics (Crolles) SASInventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
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Publication number: 20200227451Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.Type: ApplicationFiled: January 10, 2020Publication date: July 16, 2020Inventors: Laurent GAY, Frederic LALANNE, Yann HENRION, Francois GUYADER, Pascal FONTENEAU, Aurelien SEIGNARD
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Patent number: 10446593Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.Type: GrantFiled: October 26, 2018Date of Patent: October 15, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader
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Publication number: 20190252457Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: ApplicationFiled: February 8, 2019Publication date: August 15, 2019Inventors: Frederic LALANNE, Laurent GAY, Pascal FONTENEAU, Yann HENRION, Francois GUYADER
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Publication number: 20190067342Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.Type: ApplicationFiled: October 26, 2018Publication date: February 28, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader
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Patent number: 10147748Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.Type: GrantFiled: May 22, 2017Date of Patent: December 4, 2018Assignee: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader
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Publication number: 20180145100Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.Type: ApplicationFiled: May 22, 2017Publication date: May 24, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader
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Patent number: 8716843Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.Type: GrantFiled: April 25, 2012Date of Patent: May 6, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Laurent Gay, Francois Guyader, Frederic Diette
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Publication number: 20120273952Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.Type: ApplicationFiled: April 25, 2012Publication date: November 1, 2012Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.Inventors: Laurent Gay, Francois Guyader, Frederic Diette