Patents by Inventor Laurent Herard

Laurent Herard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7288843
    Abstract: A substrate, in particular, a multilayer substrate, includes a mounting and electrical-connection support, and a face for mounting at least one integrated circuit chip (IC chip). The substrate and the mounted IC chip are placed in an injection mold. The injection mold has two parts that surround the periphery of the substrate. One part of the injection mold defines a cavity for molding an encapsulation material thereby encapsulating the IC chip, and includes a face for bearing on the mounting face. At least one recess is provided in one part of the injection mold. The recess defines, above the mounting face, a slot for providing a vent for venting gases. The mounting face includes a region on which a metal outer layer is placed. The metal outer layer extends along the recess and on the bearing face on both sides of the recess.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: October 30, 2007
    Assignee: STMicroelectronics SA
    Inventors: Christophe Prior, Laurent Herard
  • Publication number: 20040075191
    Abstract: Substrate, in particular a multilayer substrate constituting a mounting and electrical-connection support, having a face (2) for mounting at least one integrated-circuit chip (3) and capable of being placed, provided with this chip, in an injection mould (8) having two parts which take between them the periphery of the substrate and one of which defines a cavity (15) for moulding an encapsulation material for the purpose of encapsulating the said chip and has a face for bearing on the said mounting face, in which at least one recess (16) is provided, the said recess defining, above the said mounting face, a slot (17) constituting a vent for venting gases. Its aforementioned mounting face (2) has a region on which a metal outer layer (6) is placed, this layer being placed so as to extend along the said recess (16) and on the said bearing face (12) on either side of this recess.
    Type: Application
    Filed: December 1, 2003
    Publication date: April 22, 2004
    Inventors: Christophe Prior, Laurent Herard
  • Patent number: 6087202
    Abstract: A process for manufacturing semiconductor packages comprising, respectively, a substrate, a chip which forms an integrated circuit and is attached to one region of the substrate, electrical connection means connecting the chip to a group of external electrical connection regions lying on one face of the substrate, as well as an encapsulation encasement. The process consists in producing, in a matrix configuration, a multiplicity of groups of connection regions (104a) on a common substrate plate (102), corresponding to as many chip attachment regions (109), in attaching a chip (103) to each attachment region (109) of the common substrate plate, in electrically connecting each chip (103) to the associated electrical connection regions (104a), so as to obtain an assembly (111) consisting of the substrate plate and the connected chips.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: July 11, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Juan Exposito, Laurent Herard, Andrea Cigada