Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.

Abstract: A processing device, operatively coupled with a memory device, is configured to receive a direct memory access (DMA) command to perform a memory access operation, the DMA command comprising a priority value; assign the DMA command to a priority queue of a plurality of priority queues based on the priority value of the DMA command; and execute a plurality of DMA commands from the plurality of priority queues according to a corresponding execution rate of each priority queue of the plurality of priority queues.

Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.

Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.

Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.

Abstract: A processing device, operatively coupled with a plurality of memory devices, is configured to receive a DMA command for a plurality of data sectors to be moved from a source memory region to a destination memory region, the destination memory region comprises a plurality of noncontiguous memory addresses and the DMA command comprises a destination value referencing the plurality of noncontiguous memory addresses. The processing device further retrieves the plurality of noncontiguous memory addresses from a location identified by the destination value. The processing device then reads the plurality of data sectors from the source memory region. The processing device also performs, for each respective data sector of the plurality of data sectors associated with the DMA command, a write operation to write the respective data sector into a corresponding respective noncontiguous memory address from the plurality of noncontiguous memory addresses of the destination memory region.

Abstract: A method is described for managing issuance of memory commands. The method includes determining whether a number of high priority commands from a cache controller meets a first threshold. In response to meeting the first threshold, a second threshold, which indicates a maximum number of low priority commands allowed in a low latency memory command queue, is set to a first value. In response to not meeting the first threshold, the second threshold is set to a second value. The method further selects a memory command for issuance from the cache controller command queue, wherein the memory command is a high priority memory command when the number of low priority memory commands stored in the low latency memory controller command queue meets the second threshold and is a low priority memory command when the number of low priority memory commands does not meet the second threshold.

Abstract: A processing device, operatively coupled with a plurality of memory devices, is configured to receive a DMA command for a plurality of data sectors to be moved from a source memory region to a destination memory region, the source memory region comprises a plurality of noncontiguous memory addresses and the DMA command comprises a source value referencing the plurality of noncontiguous memory addresses. The processing device further retrieves the plurality of noncontiguous memory addresses from a location identified by the source value. The processing device then reads the plurality of data sectors from the plurality of noncontiguous memory addresses. The processing device also writes the plurality of data sectors to the destination memory region.

Abstract: A processing device, operatively coupled with a memory device, is configured to receive a direct memory access (DMA) command to perform a memory access operation, the DMA command comprising a priority value; assign the DMA command to a priority queue of a plurality of priority queues based on the priority value of the DMA command; and execute a plurality of DMA commands from the plurality of priority queues according to a corresponding execution rate of each priority queue of the plurality of priority queues.

Abstract: A processing device, operatively coupled with a plurality of memory devices, is configured to receive a DMA command for a plurality of data sectors to be moved from a source memory region to a destination memory region, the source memory region comprises a plurality of noncontiguous memory addresses and the DMA command comprises a source value referencing the plurality of noncontiguous memory addresses. The processing device further retrieves the plurality of noncontiguous memory addresses from a location identified by the source value. The processing device then reads the plurality of data sectors from the plurality of noncontiguous memory addresses. The processing device also writes the plurality of data sectors to the destination memory region.

Abstract: A processing device, operatively coupled with a plurality of memory devices, is configured to receive a direct memory access (DMA) command for moving a plurality of data sectors from a source memory region to a destination memory region, the DMA command comprising a priority value. The processing device further assigns the DMA command to a priority queue of a plurality of priority queues based on the priority value of the DMA command, each priority queue has a corresponding set of priority values. The processing device also determines an execution rate for each priority queue of the plurality of priority queues. The processing device then executes a plurality of DMA commands from the plurality of priority queues according to the corresponding execution rate of each priority queue.

Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.