Patents by Inventor Laurent Lopez
Laurent Lopez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11680835Abstract: An oscillating analog signal includes a succession of dampened oscillations. That oscillating analog signal is conditioned to generate an output signal including only oscillations of the oscillating analog signal which have an amplitude smaller than a first threshold. The output signal is then processed by a processing unit, where the first threshold is compatible with a maximum level of voltage tolerable by the processing unit.Type: GrantFiled: January 22, 2021Date of Patent: June 20, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Laurent Lopez
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Publication number: 20230064471Abstract: A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.Type: ApplicationFiled: August 10, 2022Publication date: March 2, 2023Applicant: STMicroelectronics (Rousset) SASInventor: Laurent LOPEZ
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Patent number: 11509305Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.Type: GrantFiled: August 25, 2021Date of Patent: November 22, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Laurent Lopez
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Publication number: 20210384903Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.Type: ApplicationFiled: August 25, 2021Publication date: December 9, 2021Inventors: Nicolas Froidevaux, Laurent Lopez
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Patent number: 11133798Abstract: A device includes a first connection pin, a second connection pin, a third connection pin, and a fourth connection pin. The second connection pin is configured to be connected to a supply voltage. The fourth connection pin is configured to be coupled to a reference voltage. The device further includes a first transistor including: a first gate and a first source/drain coupled to the first connection pin; a second transistor including a second gate and a second source/drain connected to the first transistor; and a third transistor including a third gate, a third source/drain connected to the second transistor, and a fourth source/drain connected to the fourth connection pin. The third transistor is configured to be controlled by a digital signal using the third connection pin. Both the first gate and the second gate are directly connected to the second connection pin.Type: GrantFiled: April 23, 2020Date of Patent: September 28, 2021Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Nicolas Froidevaux, Laurent Lopez
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Publication number: 20210231478Abstract: An oscillating analog signal includes a succession of dampened oscillations. That oscillating analog signal is conditioned to generate an output signal including only oscillations of the oscillating analog signal which have an amplitude smaller than a first threshold. The output signal is then processed by a processing unit, where the first threshold is compatible with a maximum level of voltage tolerable by the processing unit.Type: ApplicationFiled: January 22, 2021Publication date: July 29, 2021Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas FROIDEVAUX, Laurent LOPEZ
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Publication number: 20200343890Abstract: A device comprising transistors in a series connection is disclosed. In an embodiment a device includes a first transistor, a second transistor connected to the first transistor and a third transistor connected to the second transistor, wherein the transistors are connected in a series connection, and wherein the third transistor is configured to be controlled by a digital signal.Type: ApplicationFiled: April 23, 2020Publication date: October 29, 2020Inventors: Nicolas Froidevaux, Laurent Lopez
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Patent number: 8830761Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.Type: GrantFiled: March 5, 2013Date of Patent: September 9, 2014Assignee: STMicroelectronics (Rousset) SASInventors: Francesco La Rosa, Olivier Pizzuto, Stephan Niel, Philippe Boivin, Pascal Fornara, Laurent Lopez, Arnaud Regnier
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Publication number: 20130229875Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.Type: ApplicationFiled: March 5, 2013Publication date: September 5, 2013Applicant: STMICROELECTRONICS (ROUSSET) SASInventors: Francesco La Rosa, Olivier Pizzuto, Stephan Niel, Philippe Boivin, Pascal Fornara, Laurent Lopez, Arnaud Regnier
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Publication number: 20080215664Abstract: User devices may have connectivity with a backend server only occasionally. Provided is a communication means for such user devices to operate offline, when connectivity is unavailable, and to seamlessly transition to online connectivity when it is available. At least a subset of information from the backend server is communicated to the user device to enable the user to perform functions with the device regardless if the device is online or offline. The information from the user device can be communicated to the backend server when connectivity is established and/or can be communicated based on a cost verses value analysis.Type: ApplicationFiled: March 1, 2007Publication date: September 4, 2008Applicant: MICROSOFT CORPORATIONInventors: Erik Roser Dibbern, Ricky Kaare Rasmussen, Laurent Lopez, Bjarne Schon
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Publication number: 20080215405Abstract: Applications are provided in as usable and intuitive tasks or subtasks that can be integrated with business solutions. The tasks or subtasks can be reutilized in a code or definition of the application, mitigating the amount of code and memory needed to be installed on a user device. In addition, the tasks or subtasks can be utilized across applications, further conserving device resources. The user can be presented with the tasks or subtasks in a logical flow or progression, allowing for ease of completion of the tasks.Type: ApplicationFiled: March 1, 2007Publication date: September 4, 2008Applicant: MICROSOFT CORPORATIONInventors: Erik Roser Dibbern, Ricky Kaare Rasmussen, Laurent Lopez, Bjarne Schon