Patents by Inventor Laurent Moll

Laurent Moll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9852081
    Abstract: A multi-dimension engine, connected to a system TLB, generates sequences of addresses to request page address translation prefetch requests in advance of predictable accesses to elements within data arrays. Prefetch requests are filtered to avoid redundant requests of translations to the same page. Prefetch requests run ahead of data accesses but are tethered to within a reasonable range. The number of pending prefetches are limited. A system TLB stores a number of translations, the number being relative to the dimensions of the range of elements accessed from within the data array.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: December 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Laurent Moll
  • Patent number: 9734070
    Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 15, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Alain Artieri, Subbarao Palacharla, Laurent Moll, Raghu Sankuratri, Kedar Bhole, Vinod Chamarty
  • Patent number: 9639469
    Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.
    Type: Grant
    Filed: July 13, 2013
    Date of Patent: May 2, 2017
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Laurent Moll, Jean-Jacques Lecler, Jonah Proujansky-Bell
  • Publication number: 20170116118
    Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.
    Type: Application
    Filed: October 23, 2015
    Publication date: April 27, 2017
    Inventors: ALAIN ARTIERI, SUBBARAO PALACHARLA, LAURENT MOLL, RAGHU SANKURATRI, Kedar Bhloe, Vinod Chamarty
  • Patent number: 9563560
    Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: February 7, 2017
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Laurent Moll, Jean-Jacques Lecler
  • Patent number: 9465749
    Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: October 11, 2016
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Laurent Moll, Jean-Jacques Lecler, Philippe Boucard
  • Patent number: 9396130
    Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: July 19, 2016
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Philippe Boucard, Jean-Jacques LeCler, Laurent Moll
  • Patent number: 9170949
    Abstract: A simplified coherency controller supports multiple exclusively active fully coherent agent interfaces and any number of active I/O (partially) coherent agent interfaces. A state controller determines which fully coherent agent is active. Multiple fully coherent agents can be simultaneously active during a short period of a transition of processing from one to another processor. Multiple fully coherent agents can be simultaneously active, though without a mutually consistent view of memory, which is practical in cases such as when running multiple operating systems on different processors.
    Type: Grant
    Filed: September 28, 2013
    Date of Patent: October 27, 2015
    Assignee: Qualcomm Technologies, Inc.
    Inventor: Laurent Moll
  • Patent number: 9141556
    Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 22, 2015
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Laurent Moll, Jean-Jacques LeCler, Philippe Boucard
  • Patent number: 8930638
    Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: January 6, 2015
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Laurent Moll, Jean-Jacques Lecler, Philippe Boucard
  • Patent number: 8788737
    Abstract: A system and method are disclosed for connecting PCI-ordered agents based on fully independent networks. The system and method are free of PCI topology constraints, so that the system and method can be implemented in an inexpensive and scalable way. The method disclosed is used to handle and transport PCI-ordered traffic on a fabric. Based on the actual ordering requirement of the set of PCI agents, the fabric includes two, three, or four independent networks.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: July 22, 2014
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Philippe Boucard, Jean-Jacques Lecler, Philippe Martin, Laurent Moll
  • Publication number: 20140149687
    Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.
    Type: Application
    Filed: November 27, 2012
    Publication date: May 29, 2014
    Applicant: QUALCOMM TECHNOLOGIES, INC.
    Inventors: Laurent Moll, Jean-Jacques Lecler, Philippe Boucard
  • Publication number: 20140108744
    Abstract: A simplified coherency controller supports multiple exclusively active fully coherent agent interfaces and any number of active I/O (partially) coherent agent interfaces. A state controller determines which fully coherent agent is active. Multiple fully coherent agents can be simultaneously active during a short period of a transition of processing from one to another processor. Multiple fully coherent agents can be simultaneously active, though without a mutually consistent view of memory, which is practical in cases such as when running multiple operating systems on different processors.
    Type: Application
    Filed: September 28, 2013
    Publication date: April 17, 2014
    Applicant: ARTERIS SAS
    Inventor: Laurent MOLL
  • Publication number: 20140095809
    Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.
    Type: Application
    Filed: July 13, 2013
    Publication date: April 3, 2014
    Applicant: QUALCOMM TECHNOLOGIES, INC.
    Inventors: Laurent MOLL, Jean-Jacques Lecler, Jonah Proujansky-Bell
  • Publication number: 20140095808
    Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.
    Type: Application
    Filed: July 10, 2013
    Publication date: April 3, 2014
    Applicant: ARTERIS SAS
    Inventors: Laurent MOLL, Jean-Jacques LECLER
  • Publication number: 20140095807
    Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.
    Type: Application
    Filed: July 10, 2013
    Publication date: April 3, 2014
    Applicant: Qualcomm Technologies, Inc.
    Inventors: Laurent MOLL, Jean-Jacques Lecler
  • Publication number: 20140052955
    Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.
    Type: Application
    Filed: August 17, 2013
    Publication date: February 20, 2014
    Applicant: ARTERIS SAS
    Inventors: Laurent MOLL, Jean-Jacques LECLER, Philippe BOUCARD
  • Publication number: 20140052954
    Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 20, 2014
    Applicant: ARTERIS SAS
    Inventors: Laurent MOLL, Jean-Jacques LECLER, Philippe BOUCARD
  • Publication number: 20140052956
    Abstract: A multi-dimension engine, connected to a system TLB, generates sequences of addresses to request page address translation prefetch requests in advance of predictable accesses to elements within data arrays. Prefetch requests are filtered to avoid redundant requests of translations to the same page. Prefetch requests run ahead of data accesses but are tethered to within a reasonable range. The number of pending prefetches are limited. A system TLB stores a number of translations, the number being relative to the dimensions of the range of elements accessed from within the data array.
    Type: Application
    Filed: August 17, 2013
    Publication date: February 20, 2014
    Applicant: ARTERIS SAS
    Inventor: Laurent MOLL
  • Publication number: 20140052919
    Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 20, 2014
    Applicant: ARTERIS SAS
    Inventors: Laurent MOLL, Jean-Jacques LECLER, Philippe BOUCARD