Patents by Inventor Laurent Pain
Laurent Pain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10845705Abstract: A method for forming a chemical guiding structure intended for self-assembly of a block copolymer by chemoepitaxy, where the method includes forming on a substrate a functionalisation layer made of a first polymer material having a first chemical affinity with respect to the block copolymer; forming on the substrate guiding patterns made of a second polymer material having a second chemical affinity with respect to the block copolymer, different from the first chemical affinity, and wherein the guiding to patterns have a critical dimension of less than 12.5 nm and are formed by means of a mask comprising spacers.Type: GrantFiled: December 20, 2018Date of Patent: November 24, 2020Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Raluca Tiron, Guillaume Claveau, Ahmed Gharbi, Laurent Pain, Xavier Chevalier, Christophe Navarro, Anne Paquet
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Publication number: 20190196336Abstract: A method for forming a chemical guiding structure intended for self-assembly of a block copolymer by chemoepitaxy, where the method includes forming on a substrate a functionalisation layer made of a first polymer material having a first chemical affinity with respect to the block copolymer; forming on the substrate guiding patterns made of a second polymer material having a second chemical affinity with respect to the block copolymer, different from the first chemical affinity, and wherein the guiding to patterns have a critical dimension of less than 12.5 nm and are formed by means of a mask comprising spacers.Type: ApplicationFiled: December 20, 2018Publication date: June 27, 2019Inventors: Raluca TIRON, Guillaume CLAVEAU, Ahmed GHARBI, Laurent PAIN, Xavier CHEVALIER, Christophe NAVARRO, Anne PAQUET
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Patent number: 9156306Abstract: Lithography method for etching very dense patterns on a substrate, based on a combination of several less dense partial patterns; a sacrificial layer is formed on a substrate and is etched according to a first partial pattern; spacers are formed on edges of elements of the sacrificial layer, the spacers defining a second partial pattern; then the sacrificial layer is removed leaving only the spacers remaining. A layer sensitive to an electron beam is subsequently deposited between the spacers to a thickness less than or equal to the height of the spacers, and this sensitive layer is exposed using an electron beam according to a third partial pattern such that there remains on the substrate a final pattern of regions lacking spacers and a sensitive layer, this pattern resulting from the combination of the second and third partial patterns and having higher density than each of the partial patterns.Type: GrantFiled: May 25, 2011Date of Patent: October 13, 2015Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Pain, Jerome Belledent, Sebastien Barnola
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Patent number: 8889550Abstract: A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias.Type: GrantFiled: May 25, 2011Date of Patent: November 18, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Jerome Belledent, Laurent Pain, Sebastien Barnola
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Publication number: 20130087527Abstract: Lithography method for etching very dense patterns on a substrate, based on a combination of several less dense partial patterns; a sacrificial layer is formed on a substrate and is etched according to a first partial pattern; spacers are formed on edges of elements of the sacrificial layer, the spacers defining a second partial pattern; then the sacrificial layer is removed leaving only the spacers remaining A layer sensitive to an electron beam is subsequently deposited between the spacers to a thickness less than or equal to the height of the spacers, and this sensitive layer is exposed using an electron beam according to a third partial pattern such that there remains on the substrate a final pattern of regions lacking spacers and a sensitive layer, this pattern resulting from the combination of the second and third partial patterns and having higher density than each of the partial patterns.Type: ApplicationFiled: May 25, 2011Publication date: April 11, 2013Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Pain, Jerome Belledent, Sebastien Barnola
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Publication number: 20130072017Abstract: A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias.Type: ApplicationFiled: March 25, 2011Publication date: March 21, 2013Inventors: Jerome Belledent, Laurent Pain, Sebastien Barnola
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Patent number: 8252638Abstract: A method for forming an empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.Type: GrantFiled: February 28, 2007Date of Patent: August 28, 2012Assignee: STMicroelectronics S.A.Inventors: Philippe Coronel, Yves Laplanche, Laurent Pain
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Patent number: 7955914Abstract: A method is for producing an asymmetric architecture semiconductor device. The device includes a substrate, and in stacked relation, a first photosensitive layer, a non-photosensitive layer, and a second photosensitive layer. The method includes a first step of exposing a first zone in each of the photosensitive layers by a first beam of electrons traversing the non-photosensitive layer. A second step includes exposing at least one second zone of one of the two photosensitive layers by a second beam of electrons or photons or ions, thereby producing a widening of one of the first zones compared to the other first zone such that the second zone is in part superimposed on one of the first zones.Type: GrantFiled: October 2, 2008Date of Patent: June 7, 2011Assignees: STMicroelectronics SA, Commissariat a l'Energie AtomiqueInventors: Serdar Manakli, Jessy Bustos, Philippe Coronel, Laurent Pain
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Patent number: 7897308Abstract: A method for transferring a predetermined pattern onto a flat support performed by direct writing by means of a particle beam comprises at least: deposition of a photoresist layer on a free surface of the support, application of the beam on exposed areas of the photoresist layer, performing correction by modulation of exposure doses received by each exposed area, developing of the photoresist layer so as to form said pattern. Correction further comprises determination of a substitution pattern (11) comprising at least one subresolution feature and use of the substitution pattern (11) for determining the areas to be exposed when the electron beam is applied. In addition, modulation takes account of the density of the substitution pattern (11) near to each exposed area.Type: GrantFiled: May 5, 2006Date of Patent: March 1, 2011Assignees: Commissariat a l'Energie Atomique, Freescale Semiconductor, Inc.Inventors: Laurent Pain, Serdar Manakli, Georges Bervin
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Patent number: 7767104Abstract: A fabrication method in thin layers, for example of integrated electronic circuits or MEMS. A correction method allows design errors made for example by photolithography in a thin layer to be repaired, and without necessarily having to utilize a new mask or without having to correct an erroneous mask. A lithography device allows certain of operations of such a method to be employed.Type: GrantFiled: December 15, 2004Date of Patent: August 3, 2010Assignee: Commissariat a l'Energie AtomiqueInventor: Laurent Pain
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Publication number: 20090162789Abstract: A method for transferring a predetermined pattern onto a flat support performed by direct writing by means of a particle beam comprises at least: deposition of a photoresist layer on a free surface of the support, application of the beam on exposed areas of the photoresist layer, performing correction by modulation of exposure doses received by each exposed area, developing of the photoresist layer so as to form said pattern. Correction further comprises determination of a substitution pattern (11) comprising at least one subresolution feature and use of the substitution pattern (11) for determining the areas to be exposed when the electron beam is applied. In addition, modulation takes account of the density of the substitution pattern (11) near to each exposed area.Type: ApplicationFiled: May 5, 2006Publication date: June 25, 2009Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE, FREESCALE SEMICONDUCTOR, INC.Inventors: Laurent Pain, Serdar Manakli, Georges Bervin
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Publication number: 20090093079Abstract: A method is for producing an asymmetric architecture semi-conductor device. The device includes a substrate, and in stacked relation, a first photosensitive layer, a non-photosensitive layer, and a second photosensitive layer. The method includes a first step of exposing a first zone in each of the photosensitive layers by a first beam of electrons traversing the non-photosensitive layer. A second step includes exposing at least one second zone of one of the two photosensitive layers by a second beam of electrons or photons or ions, thereby producing a widening of one of the first zones compared to the other first zone such that the second zone is in part superimposed on one of the first zones.Type: ApplicationFiled: October 2, 2008Publication date: April 9, 2009Applicant: STMicroelectronics SAInventors: Serdar Manakli, Jessy Bustos, Philippe Coronel, Laurent Pain
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Publication number: 20070190241Abstract: A fabrication method in thin layers, for example of integrated electronic circuits or MEMS. A correction method allows design errors made for example by photolithography in a thin layer to be repaired, and without necessarily having to utilize a new mask or without having to correct an erroneous mask. A lithography device allows certain of operations of such a method to be employed.Type: ApplicationFiled: December 15, 2004Publication date: August 16, 2007Applicant: Commissariat A L'Energie AtomiqueInventor: Laurent Pain
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Publication number: 20070155159Abstract: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.Type: ApplicationFiled: February 28, 2007Publication date: July 5, 2007Applicants: STMicroelectronics S.A., Commissariat A L'Ernergie AtomiqueInventors: Philippe Coronel, Yves Laplanche, Laurent Pain
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Patent number: 7202153Abstract: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.Type: GrantFiled: August 9, 2004Date of Patent: April 10, 2007Assignees: STMicroelectronics S.A., Commissariat a l'Ernergie, AtomiqueInventors: Philippe Coronel, Yves Laplanche, Laurent Pain
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Publication number: 20050037603Abstract: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.Type: ApplicationFiled: August 9, 2004Publication date: February 17, 2005Applicants: STMicroelectronics S.A., Commissariat A L'Ernergie AtomiqueInventors: Philippe Coronel, Yves Laplanche, Laurent Pain