Patents by Inventor Laurent Rene Moll

Laurent Rene Moll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11372717
    Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 28, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Loic Leloup, Laurent Rene Moll
  • Patent number: 11295803
    Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 5, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Loic Leloup, Laurent Rene Moll
  • Publication number: 20210358559
    Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 18, 2021
    Inventors: Jungwon Suh, Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine, Laurent Rene Moll
  • Publication number: 20210065772
    Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.
    Type: Application
    Filed: July 31, 2020
    Publication date: March 4, 2021
    Inventors: Jungwon SUH, Michael Hawjing LO, Dexter Tamio CHUN, Xavier Loic LELOUP, Laurent Rene MOLL
  • Publication number: 20210064463
    Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.
    Type: Application
    Filed: July 30, 2020
    Publication date: March 4, 2021
    Inventors: Jungwon SUH, Michael Hawjing LO, Dexter Tamio CHUN, Xavier Loic LELOUP, Laurent Rene MOLL
  • Patent number: 9760498
    Abstract: An electronic system for multiple agents, both coherent and non-coherent, to communicate with a hybrid cache, the hybrid cache to provide functionality associated with a cache for coherent agents in an outer shareable domain, and to provide functionality associated with a cache for non-coherent agents in a system shareable domain, the functionality provided by tag fields in cache lines stored in the hybrid cache. The tag fields are configured to indicate if a cache line of the hybrid cache belongs to at least one of a logical coherent cache or a logical system cache.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Laurent Rene Moll
  • Publication number: 20160092360
    Abstract: An electronic system for multiple agents, both coherent and non-coherent, to communicate with a hybrid cache, the hybrid cache to provide functionality associated with a cache for coherent agents in an outer shareable domain, and to provide functionality associated with a cache for non-coherent agents in a system shareable domain, the functionality provided by tag fields in cache lines stored in the hybrid cache. The tag fields are configured to indicate if a cache line of the hybrid cache belongs to at least one of a logical coherent cache or a logical system cache.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventor: Laurent Rene MOLL
  • Patent number: 9104421
    Abstract: A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: August 11, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Sagheer Ahmad, Edward L. Riegelsberger, Tony Yuhsiang Cheng, Laurent Rene Moll, Brian Keith Langendorf
  • Patent number: 9104423
    Abstract: A system and method for power management by providing advance notice of events. The method includes snooping a register of an operating system timer to determine a timer period associated with a scheduled event. A unit of a computer system is identified that is in a low power state. A wake up latency of the unit is determined that is based on the low power state. An advance period is determined based on the wake up latency. An advance notice of the operating system timer is triggered based on the timer period and the advance period to wake up the unit.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 11, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Sagheer Ahmad, Jay Kishora Gupta, Laurent Rene Moll
  • Publication number: 20140082238
    Abstract: A communication system is described providing for access to registers over a control register access bus. The system includes one or more core units including one or more addressable core registers, wherein the units are coupled to the communication bus. The system also includes one or more core clusters (CCLUSTERs) coupled to the one or more core units through the communication bus. The CCLUSTERs provide one or more gateways for transactions to and from the one or more core units. The system also includes a request ordering and coherency (ROC) unit coupled to the CCLUSTERs through the communication bus that is configured for scheduling transactions relating to the registers onto the communication bus. The system also includes the one or more addressable registers that are located in the ROC unit, the CCLUSTERs, and the one or more core units.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Sagheer Ahmad, Michael P. Cornaby, Laurent Rene Moll, Jay Kishora Gupta
  • Publication number: 20140032947
    Abstract: A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Sagheer Ahmad, Edward L. Riegelsberger, Tony Yuhsiang Cheng, Laurent Rene Moll, Brian Keith Langendorf
  • Publication number: 20130311797
    Abstract: A system and method for power management by providing advance notice of events. The method includes snooping a register of an operating system timer to determine a timer period associated with a scheduled event. A unit of a computer system is identified that is in a low power state. A wake up latency of the unit is determined that is based on the low power state. An advance period is determined based on the wake up latency. An advance notice of the operating system timer is triggered based on the timer period and the advance period to wake up the unit.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Sagheer Ahmad, Jay Kishora Gupta, Laurent Rene Moll
  • Patent number: 7240141
    Abstract: A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: July 3, 2007
    Assignee: Broadcom Corporation
    Inventors: Chun Hung Ning, Laurent Rene Moll, Kwong-Tak Chui, Shun Wai Go, Piyush Shashikant Jamkhandi
  • Patent number: 6314156
    Abstract: A space-efficient, multi-cycle barrel shifter circuit for shifting data inputted into the circuit by a shift value over multiple clock cycles which circuit includes: (a) a load module adapted to receive a load signal and the data, the load module coupled to the shift module and configured to load the data into the shift module upon receipt of a load signal; (b) a register module coupled to the shift module and to the load module, where the register module is a register adapted to receive a clock signal and configured to pass the data through the shift module with each clock cycle; (c) a constant shift module coupled to the register module and the shift module and configured to shift the data by a constant amount with each clock cycle; and (d) a control module coupled to the shift module and the load module, the control module capable of generating a command signal for each elementary shifter in the shift module for each clock cycle based upon the shift value, the command signal determining the amount of shift
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: November 6, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Laurent René Moll, Michael D. Mitzenmacher
  • Patent number: 6292762
    Abstract: A method determines a random permutation of input lines that produced a permuted set of bits in a bitstream. In a source design, the method replaces a logic element whose input lines are permutable with a test function. The source design is processed by a design tool to generate the bitstream including the permuted set of bits. The test function is probed with test values, and the probe results are compared with the permuted set of bits to discover the permutation of the set of bits. The test values can include a message.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: September 18, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Laurent Rene Moll, Michael David Mitzenmacher, Andrei Z. Broder, Mark Alexander Shand