Patents by Inventor Laurent Robert Chouraki

Laurent Robert Chouraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10482211
    Abstract: In an electronic circuit design system, a physical layout of at least part of an electronic circuit design is visually rendered. Magnitude of current loading are determined at one or more of the circuit nodes, or one or more clusters of nodes grouped according to predetermined clustering criteria, for a selected net or nets. The range of magnitudes is mapped to at least one gradation range for visual indicia of preselected type, such as a predetermined color spectrum; preferably, alternative gradation ranges respectively for current sources and current sinks are provided. The visual indicia of the current loading magnitudes are then adaptively displayed to overlay the corresponding circuit nodes or clusters in the rendered physical layout, providing a reference for a designer to proportionately size segments of the selected net or nets, as well as spacing required for the segments.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: November 19, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Laurent Rene Saint-Marcel, Laurent Robert Chouraki, Alexandre Roger Maurice Soyer