Abstract: A clock signal filtering circuit includes a bistable flip-flop and a controller for controlling state changes of the flip-flop. A first activation circuit activates the controller by edges of non-filtered clock signal pulses when their duration exceeds a first threshold. The first threshold is equal to a half-period corresponding to an upper frequency limit of the clock signal. A second activation circuit activates the controller by edges of filtered clock signal pulses delayed by an amount equal to a half period corresponding to a lower frequency limit of the clock signal. The clock filtering circuit transmits a filtered clock signal at a frequency within a specification interval, and at a duty cycle equal to 0.5 for a variety of different circumstances.

Abstract: A digital signal output circuit is provided. The digital signal output circuit includes capacitor forming means connected as an integrator, charging means, discharging means, means for selectively coupling, and a digital signal output. The charging means selectively charges the capacitor forming means with a constant charging current, and the discharging means selectively discharges the capacitor forming means with a constant discharging current. The means for selectively coupling selectively couples the capacitor forming means to the charging means and to the discharging means as a function of data to be transmitted by the digital signal. Additionally, the digital signal output is coupled to the capacitor forming means so as to establish a rising edge of the digital signal when the capacitor forming means is coupled to the charging means and a falling edge of the digital signal when the capacitor forming means is coupled to the discharging means.

Abstract: An option configuration device in an integrated circuit including, for each option bit to be configured, a configuration stage that includes a first set of non-volatile memory cells parallel-connected between a first node and a ground connection, and a second set of non-volatile memory cells parallel-connected between a second node and a ground connection. The first and second nodes are each connected to an input of a read circuit including a differential amplifier.

Abstract: An electrically programmable non-volatile memory integrated circuit includes: read/write resources; a first bit line; a second bit line; an option configuration register consisting of at least one bit; a reading mechanism; and a writing mechanism. The option configuration register includes, for the at least one bit: a bistable element including at least one memory cell, and a static memory element. The at least one memory cell is coupled to the first bit line and to the second bit line, and the static memory element is coupled to the bistable element. The reading mechanism is for reading a state of the static memory element, and it utilizes the first and second bit lines and the read/write resources. The writing mechanism is for setting the state of the static memory element, and it utilizes the first and second bit lines and the read/write resources.