Patents by Inventor Laurent ROUGE

Laurent ROUGE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190227120
    Abstract: Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.
    Type: Application
    Filed: April 4, 2019
    Publication date: July 25, 2019
    Inventors: Laurent ROUGE, Julien EYDOUX, Marcello GIUFFRE
  • Publication number: 20180275193
    Abstract: Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.
    Type: Application
    Filed: October 7, 2016
    Publication date: September 27, 2018
    Inventors: Laurent ROUGE, Julien EYDOUX, Marcello GIUFFRE
  • Publication number: 20180269880
    Abstract: A programmable logic block for a FPGA comprises two Lookup Tables (LUT). The configuration information for these LUTs is provided by a programmable controller, which itself incorporates LUT functionality. This intermediate layer of LUT functionality provides a means to programmatically control the behaviour of the primary LUTs in an operational mode, on the basis of settings made during an initialization mode. Certain embodiments also incorporate a Logic circuit, which together with the programmable behaviour of the Primary LUTs provides a means for efficiently implementing a number of common logic functions in including adders, multiplexers, parity and extended LUT and Multiplexer functions. A method for programming an FPGA comprising such a programmable logic block and corresponding data stream are also described.
    Type: Application
    Filed: October 7, 2016
    Publication date: September 20, 2018
    Inventors: Laurent ROUGE, Julien EYDOUX, Serge Alexandre MARTHELY