Patents by Inventor Laurent Stadler

Laurent Stadler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for bus mastering for devices resident in configurable system logic
    Patent number: 7107374
    Abstract: A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a second set of signal lines to receive a grant associated with the data transfer request. A bus master unit (BMU) is coupled with the CSL through the first set of signal lines and the second set of signal lines. The BMU is connected to the CSI bus. The BMU arbitrates to take control of the CSI bus on behalf of the CSL enabling the CSL to perform data transfer to or from the CSI bus bypassing the processor.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: September 12, 2006
    Assignee: XILINX, Inc.
    Inventor: Laurent Stadler
  • Method for delivering packet boundary or other metadata to and from a device using direct memory controller
    Patent number: 6889266
    Abstract: An existing field of a descriptor is used to store metadata associated with a block of data to be transferred. The metadata is sent to a device using a special command when transferring the block of data from a memory to the device. The metadata is sent to the device using an existing bus. The metadata is sent to the device from the field of the descriptor. The metadata may carry packet boundary information, transmit status information, or receive status information.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: May 3, 2005
    Assignee: Xilinx, Inc.
    Inventor: Laurent Stadler