Patents by Inventor Laurent Tabaries

Laurent Tabaries has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7613208
    Abstract: An interface communicates between two communication buses which use at least two different protocols. The interface includes a volatile memory having at least two access ports and including two transcoding circuits, each transcoding circuit being specific to each of the protocols to be interfaced.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: November 3, 2009
    Assignee: STMicroelectronics
    Inventors: Herve Chalopin, Laurent Tabaries
  • Patent number: 7600068
    Abstract: A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has been programmed, the processor launches the start of the sequence and the programmable interface manages and controls in a standalone manner the inputs/outputs with the slave circuit. The management and control of the slave circuit is independent of any interrupt specific to the system. The programmable interface uses a software-type upgrade to interface with new slave circuits that may appear on the market.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: October 6, 2009
    Assignee: STMicroelectronics S.A
    Inventors: Herve Chalopin, Laurent Tabaries
  • Patent number: 7386645
    Abstract: An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2?P?N and 1?Q?N. In the event of a plurality of conflicting requests to access a common resource originating from a plurality of respective initiator modules, an arbitration unit grants an exclusive right of access to the resource to a defined one of these initiator modules. The arbitration unit is constructed either to apply a standard arbitration mechanism to these respective initiators, or to apply as a priority a specific arbitration mechanism only to the members of a subset of these initiator modules, for each of which it receives a linked privileged access signal.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: June 10, 2008
    Assignee: STMicroelectronics SA
    Inventors: Herve Chalopin, Laurent Tabaries
  • Patent number: 7325088
    Abstract: An electronic system comprises a control unit for ordering the storage of an index value for indexed registers, in an additional index register linked to a defined initiator module, in response to a request to write the index value in an index register linked to the indexed registers, initiated by the initiator module. In response to any request to access an indexed register initiated by a defined initiator module, the control unit copies the index value from the additional index register linked to this initiator module to the index register linked to this indexed register, prior to execution of the access request. This enables management of access to indexed registers associated with an arbitration mechanism provided for managing conflicting access requests initiated by different functional modules in a system on a chip.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: January 29, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Hervé Chalopin, Laurent Tabaries
  • Patent number: 7313646
    Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication protocols of the initiator module and of the target module. The interface and control module is constructed to set a composite instruction detection signal in response to the detection of a composite instruction executed by the initiator module, which composite instruction detection signal is used for the interfacing. The interface and control module is constructed to detect a composite instruction executed by the initiator module when, at a determined clock cycle of the initiator module, a change of the elementary operation executed by the initiator module is detected with respect to the previous clock cycle of the initiator module, while, at the same time, a signal for selecting the target module which was active is kept active.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: December 25, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Hervé Chalopin, Laurent Tabaries
  • Patent number: 7209988
    Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module. The initiator module is activated by edges of an activation signal generated from a first clock signal having a frequency. A control module is activated by edges of a second clock signal having a frequency, which is at least twice as large as the frequency of the first clock signal. The control module is constructed so as, in response to an request for access to the target module, initiated by the initiator module on an active edge of the activation signal, to set a signal for blocking the activation signal before the next edge of the latter, and to reinitialize the blocking signal on the first active edge of the first clock signal which follows the indication by the target module that the processing of the request is terminated at the target module.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: April 24, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Hervé Chalopin, Laurent Tabaries
  • Publication number: 20060095692
    Abstract: A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has been programmed, the processor launches the start of the sequence and the programmable interface manages and controls in a standalone manner the inputs/outputs with the slave circuit. The management and control of the slave circuit is independent of any interrupt specific to the system. The programmable interface uses a software-type upgrade to interface with new slave circuits that may appear on the market.
    Type: Application
    Filed: September 1, 2005
    Publication date: May 4, 2006
    Applicant: STMicroelectronics S.A.
    Inventors: Herve Chalopin, Laurent Tabaries
  • Publication number: 20060056450
    Abstract: An interface communicates between two communication buses which use at least two different protocols. The interface includes a volatile memory having at least two access ports and including two transcoding circuits, each transcoding circuit being specific to each of the protocols to be interfaced.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 16, 2006
    Applicant: STMicroelectronics S.A.
    Inventors: Herve Chalopin, Laurent Tabaries
  • Publication number: 20060022710
    Abstract: A circuit disposes of a power supply terminal dedicated to the power supply VIO of the input/output terminals in order that these terminals may be used by a customer in a voltage range of their choice. The input/output terminals produced according to the invention include transposition means that allow the voltage of the signal flowing through them to be adapted from a first voltage range to a second voltage range.
    Type: Application
    Filed: June 28, 2005
    Publication date: February 2, 2006
    Applicant: STMicroelectronics SA
    Inventors: Herve Chalopin, Laurent Tabaries
  • Publication number: 20060010280
    Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication protocols of the initiator module and of the target module. The interface and control module is constructed to set a composite instruction detection signal in response to the detection of a composite instruction executed by the initiator module, which composite instruction detection signal is used for the interfacing. The interface and control module is constructed to detect a composite instruction executed by the initiator module when, at a determined clock cycle of the initiator module, a change of the elementary operation executed by the initiator module is detected with respect to the previous clock cycle of the initiator module, while, at the same time, a signal for selecting the target module which was active is kept active.
    Type: Application
    Filed: May 26, 2005
    Publication date: January 12, 2006
    Applicant: STMicroelectronics S.A.
    Inventors: Herve Chalopin, Laurent Tabaries
  • Publication number: 20050268013
    Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module. The initiator module is activated by edges of an activation signal generated from a first clock signal having a frequency. A control module is activated by edges of a second clock signal having a frequency, which is at least twice as large as the frequency of the first clock signal. The control module is constructed so as, in response to an request for access to the target module, initiated by the initiator module on an active edge of the activation signal, to set a signal for blocking the activation signal before the next edge of the latter, and to reinitialize the blocking signal on the first active edge of the first clock signal which follows the indication by the target module that the processing of the request is terminated at the target module.
    Type: Application
    Filed: May 12, 2005
    Publication date: December 1, 2005
    Applicant: STMicroelectronics SA
    Inventors: Herve Chalopin, Laurent Tabaries
  • Publication number: 20050256992
    Abstract: An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2?P?N and 1?Q?N. In the event of a plurality of conflicting requests to access a common resource originating from a plurality of respective initiator modules, an arbitration unit grants an exclusive right of access to the resource to a defined one of these initiator modules. The arbitration unit is constructed either to apply a standard arbitration mechanism to these respective initiators, or to apply as a priority a specific arbitration mechanism only to the members of a subset of these initiator modules, for each of which it receives a linked privileged access signal.
    Type: Application
    Filed: May 2, 2005
    Publication date: November 17, 2005
    Applicant: STMicroelectronics S.A.
    Inventors: Herve Chalopin, Laurent Tabaries
  • Publication number: 20050256993
    Abstract: An electronic system comprises a control unit for ordering the storage of an index value for indexed registers, in an additional index register linked to a defined initiator module, in response to a request to write the index value in an index register linked to the indexed registers, initiated by the initiator module. In response to any request to access an indexed register initiated by a defined initiator module, the control unit copies the index value from the additional index register linked to this initiator module to the index register linked to this indexed register, prior to execution of the access request. This enables management of access to indexed registers associated with an arbitration mechanism provided for managing conflicting access requests initiated by different functional modules in a system on a chip.
    Type: Application
    Filed: May 2, 2005
    Publication date: November 17, 2005
    Applicant: STMicroelectronics S.A.
    Inventors: Herve Chalopin, Laurent Tabaries