Patents by Inventor Laurent Vallier

Laurent Vallier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11380543
    Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 5, 2022
    Assignees: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITÉ GRENOBLE ALPES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Pierre-Edouard Raynal, Pascal Besson, Jean-Michel Hartmann, Virginie Loup, Laurent Vallier
  • Publication number: 20200194259
    Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 18, 2020
    Applicants: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITÉ GRENOBLE ALPES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Pierre-Edouard RAYNAL, Pascal BESSON, Jean-Michel HARTMANN, Virginie LOUP, Laurent VALLIER
  • Patent number: 10062602
    Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 28, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS—Centre National de la Recherche Scientifique, APPLIED MATERIALS, Inc
    Inventors: Nicolas Posseme, Sebastien Barnola, Olivier Joubert, Srinivas Nemani, Laurent Vallier
  • Patent number: 9583339
    Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: February 28, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS-Centre National de la Recherche Scientifique, APPLIED MATERIALS, Inc.
    Inventors: Nicolas Posseme, Thibaut David, Olivier Joubert, Thorsten Lill, Srinivas Nemani, Laurent Vallier
  • Patent number: 9570317
    Abstract: A microelectronic method for etching a layer to be etched, including: modifying the layer to be etched from a surface of the layer to be etched and over a depth corresponding to at least a portion of thickness of the layer to be etched to form a film, with the modifying including implanting light ions into the layer to be etched; and removing the film includes a selective etching of the film relative to at least one layer underlying the film.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 14, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE JOSEPH FOURIER
    Inventors: Nicolas Posseme, Olivier Joubert, Laurent Vallier
  • Publication number: 20160300709
    Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.
    Type: Application
    Filed: April 6, 2016
    Publication date: October 13, 2016
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS Centre National de la Recherche Scientifique, APPLIED MATERIALS, Inc.
    Inventors: Nicolas POSSEME, Thibaut David, Olivier Joubert, Thorsten Lill, Srinivas Nemani, Laurent Vallier
  • Publication number: 20160035581
    Abstract: A microelectronic method for etching a layer to be etched, including: modifying the layer to be etched from a surface of the layer to be etched and over a depth corresponding to at least a portion of thickness of the layer to be etched to form a film, with the modifying including implanting light ions into the layer to be etched; and removing the film includes a selective etching of the film relative to at least one layer underlying the film.
    Type: Application
    Filed: December 20, 2013
    Publication date: February 4, 2016
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE JOSEPH FOURIER
    Inventors: Nicolas POSSEME, Olivier JOUBERT, Laurent VALLIER
  • Patent number: 9048011
    Abstract: The invention relates to the field of production in thin coatings of electronic devices and/or MEMS and relates to an improved method for forming a pattern in a thin SiARC anti-reflective coating, comprising the doping by deposition of such SiARC coating covered with a resist pattern through a protective coating of the resist pattern, then etching the doped zones of the SiARC coating (FIG. 3c).
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 2, 2015
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS—CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE JOSEPH FOURIER
    Inventors: Nicolas Posseme, Olivier Joubert, Laurent Vallier
  • Patent number: 8956886
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Samer Banna, Olivier Joubert, Lei Lian, Maxime Darnon, Nicolas Posseme, Laurent Vallier
  • Publication number: 20140273297
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: SAMER BANNA, OLIVIER JOUBERT, LEI LIAN, MAXIME DARNON, NICOLAS POSSEME, LAURENT VALLIER
  • Publication number: 20140187046
    Abstract: The invention relates to a method for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, comprising a step of forming a layer of nitride covering the transistor gate, the method being characterized in that it comprises: after the step of forming the layer of nitride, at least one step of modifying the layer of nitride by implantation of light ions in the layer of nitride in order to form a modified layer of nitride, the step of modification being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate, the step of modifying the layer of nitride by implantation being performed using a plasma comprising the light ions; at least one step of removing the modified layer of nitride by means of a selective etching of the modified layer of nitride vis-à-vis said semiconductor material and vis-à-vis the non-modified layer of nitride
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, APPLIED MATERIALS, Inc., CNRS Centre National de la Recherche Scientifique
    Inventors: Nicolas POSSEME, Thibaut DAVID, Olivier JOUBERT, Torsten LILL, Srinivas NEMANI, Laurent VALLIER
  • Publication number: 20140183159
    Abstract: The invention relates to the field of production in thin coatings of electronic devices and/or MEMS and relates to an improved method for forming a pattern in a thin SiARC anti-reflective coating, comprising the doping by deposition of such SiARC coating covered with a resist pattern through a protective coating of the resist pattern, then etching the doped zones of the SiARC coating (FIG. 3c).
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, Universite Joseph Fourier, CNRS-Centre National de la Recherche Scientifique
    Inventors: Nicolas POSSEME, Olivier JOUBERT, Laurent VALLIER
  • Publication number: 20140187035
    Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, APPLIED MATERIALS, Inc., CNRS Centre National de la Recherche Scientifique
    Inventors: Nicolas POSSEME, Sebastien BARNOLA, Olivier JOUBERT, Srinivas NEMANI, Laurent VALLIER
  • Patent number: 6818488
    Abstract: The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching, b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material, c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: November 16, 2004
    Assignees: Commissariat a l'Energie Atomique, Centre National de la Recherche
    Inventors: Olivier Joubert, Giles Cunge, Johann Foucher, David Fuard, Marceline Bonvalot, Laurent Vallier
  • Publication number: 20040104411
    Abstract: The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps:
    Type: Application
    Filed: September 8, 2003
    Publication date: June 3, 2004
    Inventors: Olivier Joubert, Giles Cunge, Johann Foucher, David Fuard, Marceline Bonvalot, Laurent Vallier
  • Patent number: 6551698
    Abstract: Method for preparing a silicon substrate to form a thin electric insulating layer (24), characterized in that it comprises: a deoxidation step of at least one part of the silicon substrate (10), then a heat treatment step of the substrate at a temperature of 750° C. or less, the heat treatment being conducted in a NO-containing atmosphere at a pressure of 5.103 Pa (50 mBr) or less, in order to form a layer of silicon oxynitride (22) on the substrate. Use for the production of EPROM and DRAM memories.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: April 22, 2003
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Martin, Daniel Bensahel, Caroline Hernandez, Laurent Vallier