Abstract: A method for adjusting common mode rejection ratio (CMRR) and gain error of a current sense (CS) amplifier, comprising: measuring a first referred to input (RTI) offset voltage while presenting a given common mode (CM) input voltage; adding a first trim resistor of a plurality of selectable trim resistors within an adjustable feedback resistor chain to a feedback electrical path; measuring a second RTI offset voltage while presenting the given CM input voltage; estimating, based upon the first and second RTI offset voltages, a third RTI offset voltage value that would result by adding a second trim resistor of the plurality of selectable trim resistors to the feedback electrical path; using the first, second and third RTI offset voltage values to identify the combination of selectable trim resistors that achieves an RTI offset voltage closest to zero volts; and adding the identified selectable trim resistors to the feedback electrical path.

Abstract: Current sense amplifiers with extended input common mode (CM) voltage range, including an extended CM input voltage amplifier that includes a low voltage (LV) p-type metal oxide semiconductor (PMOS) input module coupled to a positive supply rail, wherein said supply rail provides a voltage that is the maximum between a positive input signal (IN+) applied to the amplifier and an internal power supply voltage. The amplifier further includes a voltage regulator coupled to the supply rail that generates a decreased voltage level relative to the supply rail voltage that is provided to the LV PMOS input module via a high voltage ground (HV_GND) line. At least part of the LV PMOS input module is powered by a voltage difference between the positive supply rail and the HV_GND line. The voltage regulator maintains said voltage difference within an operating range of LV devices within the LV PMOS input module.

Abstract: Current sense amplifiers with extended input common mode (CM) voltage range, including an extended CM input voltage amplifier that includes a low voltage (LV) p-type metal oxide semiconductor (PMOS) input module coupled to a positive supply rail, wherein said supply rail provides a voltage that is the maximum between a positive input signal (IN+) applied to the amplifier and an internal power supply voltage. The amplifier further includes a voltage regulator coupled to the supply rail that generates a decreased voltage level relative to the supply rail voltage that is provided to the LV PMOS input module via a high voltage ground (HV_GND) line. At least part of the LV PMOS input module is powered by a voltage difference between the positive supply rail and the HV_GND line. The voltage regulator maintains said voltage difference within an operating range of LV devices within the LV PMOS input module.

Abstract: A method for adjusting common mode rejection ratio (CMRR) and gain error of a current sense (CS) amplifier, comprising: measuring a first referred to input (RTI) offset voltage while presenting a given common mode (CM) input voltage; adding a first trim resistor of a plurality of selectable trim resistors within an adjustable feedback resistor chain to a feedback electrical path; measuring a second RTI offset voltage while presenting the given CM input voltage; estimating, based upon the first and second RTI offset voltages, a third RTI offset voltage value that would result by adding a second trim resistor of the plurality of selectable trim resistors to the feedback electrical path; using the first, second and third RTI offset voltage values to identify the combination of selectable trim resistors that achieves an RTI offset voltage closest to zero volts; and adding the identified selectable trim resistors to the feedback electrical path.