Patents by Inventor Laurentiu Vasiliu
Laurentiu Vasiliu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8969141Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.Type: GrantFiled: March 15, 2013Date of Patent: March 3, 2015Assignee: Broadcom CorporationInventor: Laurentiu Vasiliu
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Patent number: 8399959Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.Type: GrantFiled: May 30, 2007Date of Patent: March 19, 2013Assignee: Broadcom CorporationInventor: Laurentiu Vasiliu
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Patent number: 8110876Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.Type: GrantFiled: November 17, 2009Date of Patent: February 7, 2012Assignee: Broadcom CorporationInventors: Hung-Sung Li, Laurentiu Vasiliu
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Patent number: 8089821Abstract: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.Type: GrantFiled: January 18, 2010Date of Patent: January 3, 2012Assignee: Broadcom CorporationInventors: Jonathan Alois Schmitt, Laurentiu Vasiliu, Myron Buer
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Patent number: 8040748Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.Type: GrantFiled: September 28, 2009Date of Patent: October 18, 2011Assignee: Broadcom CorporationInventors: Myron Buer, Jonathan Schmitt, Laurentiu Vasiliu
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Publication number: 20100128403Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.Type: ApplicationFiled: November 17, 2009Publication date: May 27, 2010Applicant: Broadcom CorporationInventors: Hung-Sung Li, Laurentiu Vasiliu
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Publication number: 20100118584Abstract: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.Type: ApplicationFiled: January 18, 2010Publication date: May 13, 2010Inventors: Jonathan Alois Schmitt, Laurentiu Vasiliu, Myron Buer
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Patent number: 7715265Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.Type: GrantFiled: October 31, 2007Date of Patent: May 11, 2010Assignee: Broadcom CorporationInventors: Myron Buer, Jonathan Schmitt, Laurentiu Vasiliu
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Publication number: 20100014340Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.Type: ApplicationFiled: September 28, 2009Publication date: January 21, 2010Applicant: Broadcom CorporationInventors: Myron Buer, Jonathan Schmitt, Laurentiu Vasiliu
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Patent number: 7649798Abstract: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.Type: GrantFiled: August 17, 2006Date of Patent: January 19, 2010Assignee: Broadcom CorporationInventors: Jonathan Alois Schmitt, Laurentiu Vasiliu, Myron Buer
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Patent number: 7622775Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.Type: GrantFiled: August 29, 2006Date of Patent: November 24, 2009Assignee: Broadcom CorporationInventors: Hung-Sung Li, Laurentiu Vasiliu
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Patent number: 7609578Abstract: A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell.Type: GrantFiled: October 31, 2007Date of Patent: October 27, 2009Assignee: Broadcom CorporationInventors: Myron Buer, Jonathan Schmitt, Laurentiu Vasiliu
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Patent number: 7561456Abstract: According to one exemplary embodiment, a memory array includes a memory cell having a programmable poly fuse coupled between a designated program node and a ground node, where the programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. In the programmable poly fuse, the P type resistive poly segment is coupled to the ground node and the N type resistive poly segment is coupled to the designated program node. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to the ground node. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to the designated program node.Type: GrantFiled: May 30, 2007Date of Patent: July 14, 2009Assignee: Broadcom CorporationInventor: Laurentiu Vasiliu
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Publication number: 20090109723Abstract: A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: Broadcom CorporationInventors: Myron BUER, Jonathan Schmitt, Laurentiu Vasiliu
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Publication number: 20090109724Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: Broadcom CorporationInventors: Myron BUER, Jonathan Schmitt, Laurentiu Vasiliu
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Publication number: 20080296727Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Inventor: Laurentiu Vasiliu
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Publication number: 20080298112Abstract: According to one exemplary embodiment, a memory array includes a memory cell having a programmable poly fuse coupled between a designated program node and a ground node, where the programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. In the programmable poly fuse, the P type resistive poly segment is coupled to the ground node and the N type resistive poly segment is coupled to the designated program node. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to the ground node. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to the designated program node.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Inventor: Laurentiu Vasiliu
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Publication number: 20080043509Abstract: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.Type: ApplicationFiled: August 17, 2006Publication date: February 21, 2008Inventors: Jonathan Alois Schmitt, Laurentiu Vasiliu, Myron Buer
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Publication number: 20060289937Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.Type: ApplicationFiled: August 29, 2006Publication date: December 28, 2006Applicant: Broadcom CorporationInventors: Hung-Sung Li, Laurentiu Vasiliu
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Patent number: 7138836Abstract: A method of preventing Hot Carrier Injection in input/output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can tolerate. By placing input/output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. A circuit for preventing Hot Carrier Injection in these input/output devices comprises comparing an input voltage to a reference voltage, and if conditions that would produce Hot Carrier Injection are present (e.g. when input voltage is greater than reference voltage), slowing the turn-on of one of the series connected input/output devices, thereby reducing the voltage from the drain-to-source of another series connected input/output device.Type: GrantFiled: December 3, 2002Date of Patent: November 21, 2006Assignee: Broadcom CorporationInventors: Janardhanan S. Ajit, Laurentiu Vasiliu