Abstract: Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the A output of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

Abstract: Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.

Abstract: A system for controlling a hold-margin in a semiconductor memory device includes a programmable RC network communicatively coupled to a delay logic circuit, a latch clock generator and a latch circuit. A delay associated with a clock path is induced using a combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. A delay associated with the data path is induced using a combination of the delay logic circuit and at least one of the load cell and a wire routed across at least one of a column and a row of the semiconductor memory device. The system controls the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.