Abstract: A Web-based integrated circuit design system, method and computer program product tool allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a wealth of data and services. The services and data include competing standard architectures and reference designs. The integrated circuit design tool allows users (e.g., design engineers) to efficiently design cores and systems-on-a-chip (SOCs). The integrated circuit design tool is a “virtual lab” which allows and aides design engineers at every stage of IC product design—architecture choice, implementation options, software development, and hardware design.

Abstract: A Web-based integrated circuit design system, method and computer program product tool allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a wealth of data and services. The services and data include competing standard architectures and reference designs. The integrated circuit design tool allows users (e.g., design engineers) to efficiently design cores and systems-on-a-chip (SOCs). The integrated circuit design tool is a “virtual lab” which allows and aides design engineers at every stage of IC product design—architecture choice, implementation options, software development, and hardware design.

Abstract: A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

Abstract: A single-ended sense amplifier circuit for sensing the state of a bitline in a memory array. The sense amplifier includes an output circuit having an input and an output, the output for indicating a state of the bitline in response to a bitline voltage level. A precharge circuit is coupled to the input for charging the input to a first voltage level when the input is decoupled from the bitline. A discharge circuit is coupled between the bitline and the input. In one embodiment, the discharge circuit includes a field effect transistor coupled as a cascode device for coupling and decoupling the input to the bitline. The discharge circuit couples the input to the bitline when the discharge voltage level exceeds a threshold voltage level of the discharge circuit.

Abstract: A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

Abstract: A single-ended sense amplifier circuit for sensing the state of a bitline in a read-only memory. The sense amplifier includes an output circuit having an input and an output, the output for indicating a state of the bitline in response to a bitline voltage level. A precharge circuit is coupled to the input for charging the input to a first voltage level when the input is decoupled from the bitline. A discharge circuit is coupled between the bitline and the input. In one embodiment, the discharge circuit includes a field effect transistor coupled as a cascode device for coupling and decoupling the input to the bitline. The discharge circuit couples the input to the bitline when the discharge voltage level exceeds a threshold voltage level of the discharge circuit.

Abstract: A fast static logic gate contains a pullup logic network and a pulldown logic network configured to implement a logic function. The pullup logic network is coupled to receive gate inputs, and generates a first voltage level at a first node to represent a first state in accordance with the gate inputs and logic function. The first voltage level is less than the source voltage for the fast static logic gate circuit. A leaker circuit generates a second voltage level at the first node in response to a second state of the logic function. A driver circuit is coupled to a second node for generating an output. The pulldown logic network receives the gate inputs, and generates a second voltage level for the output to represent the second state in accordance to the gate inputs and logic function. The switch circuit couples the first node to the second node when the logic function generates the second state, and couples the source voltage to the second node when the logic function generates the first state.

Abstract: A noise suppression circuit for a floating bus in a digital integrated circuit includes pull-up and pull-down feedback loops each connected to the floating bus. The pull-up feedback loop includes a PMOS device connected between a high logic level and the floating bus, with a NOR gate switching the PMOS device. The pull-down feedback loop includes an NMOS device connected between a low logic level and the floating bus, with a NAND gate switches the NMOS device. The NOR and NAND gates are configured such that one of their inputs is connected directly to the floating bus and the other input is connected to the floating bus through an inverter having a finite gate delay. Voltage transitions occurring on the floating bus due to noise injection drive the bus back to its original state before the finite gate delay of the inverter.

Abstract: A BiCMOS circuit, with protection against a negative base-emitter voltage, is described. The bipolar device is typically coupled between, for example, V.sub.DD and an output. An input is coupled to the base of the bipolar device, turning it on or off. CMOS circuitry is included which isolates the base of the bipolar device from the input when the input goes low and discharges the base through the output. Additional circuitry is disclosed which causes the output to float whenever an enable line is low and causes the output to be at either the same or inverted logic state as the input whenever the enable line is high, to form a non-inverting or inverting tri-state buffer, respectively.

Abstract: A BiCMOS logic circuit which implements single stage inverting and non-inverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and the non-inverting output nodes. The pull-down assembly means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration provides the inverting output while driving the gate of a n-channel transistor coupled between the non-inverting output node and V.sub.ss.

Abstract: A programmable sense amplifier in accordance with the present invention includes an input multiplexer which receives a plurality of data input signals from the column lines of a ROM and provides a selected one of a data input signals as a data output signal based on control signals proviced to the input multiplexer. The voltage level of the data output signal corresponds to the number of 1's contained in the selected column line. A sensing stage receives the data output signal and amplifies it. The amplified signal is then provided to an XOR gate which either does or does not invert the amplified signal, based upon the state of the select node to which one of the XOR gate inputs is connected. The state of the select node is determined by a programmable internal multiplexer. The internal multiplexer comprises a number of FET switching transistors corresponding to the number of data input signals. Each of the switching transistors has one of its electrode areas commonly-connected to the select node.