Patents by Inventor Lawrence A. Bair

Lawrence A. Bair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10452554
    Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: October 22, 2019
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Ihab Amer, Khaled Mammou, Haibo Liu, Edward Harold, Fabio Gulino, Samuel Naffziger, Gabor Sines, Lawrence A. Bair, Andy Sung, Lei Zhang
  • Publication number: 20170293564
    Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 12, 2017
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ihab Amer, Khaled Mammou, Haibo Liu, Edward Harold, Fabio Gulino, Samuel Naffziger, Gabor Sines, Lawrence A. Bair, Andy Sung, Lei Zhang
  • Publication number: 20170092712
    Abstract: Various through silicon via capacitors and methods of fabricating the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor substrate with a portion doped with a first impurity type and a doped region of a second impurity type in the portion of the semiconductor substrate. The doped region is operable to function as a first capacitor plate. A first via hole is in the doped region. The first via hole has a first sidewall. A first insulating layer is on the first sidewall. The first insulating layer is operable to function as a capacitor dielectric. A first conductive via is in the first via hole. The first conductive via is operable to function as a second capacitor plate.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Joseph R. Siegel, Lawrence A. Bair, Bryan Black, Michael Su
  • Patent number: 7062850
    Abstract: A method of forming an electrical conductor, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigraation-inhibiting material is deposited over the planar surface and into the windows to provide electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments. Embodiments of the method may be employed in manufacture of integrated circuit conductor.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: June 20, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement, Bruce Gieseke
  • Patent number: 6904675
    Abstract: A method is provided for forming an electrical conductors, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigration-inhibiting material is deposited over the planar surface and into the windows to provide, electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: June 14, 2005
    Assignee: Hewlett-Packard Development, L.P.
    Inventors: Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement, Bruce Gieseke
  • Publication number: 20040071991
    Abstract: A method is provided for forming integrated circuit electrical conductors with electromigration-inhibiting/electrically conductive plugs disposed between electrically conductive segments of the electrical conductor. In accordance with such method, windows are formed within a planar surface. An electromigration-inhibiting/electrically conductive material is deposited over the planar surface and through the windows to fill the windows and thereby provide, in such windows, plugs of electromigration-inhibiting/electrically conductive material. Portions of the electromigration-inhibiting/electrically conductive material are removed to form the plugs with surfaces co-planar a surface surrounding the plugs. The electrical conductive segments are formed within the same planar surface as the plugs, either before, or after the plug formation. The electrical conductive segments have surfaces co-planar with the plugs, are aligned with and electrically interconnected through the plugs.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 15, 2004
    Inventors: Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement, Bruce Gieseke
  • Patent number: 6678951
    Abstract: A method is provided for forming an electrical conductors, comprising forming electrically conductive segments incorporating electromigration-inhibiting plugs. A row of windows is formed in a planar surface and electromigration-inhibiting material is deposited over the planar surface and into the windows to provide electromigration-inhibiting plugs in the windows. The plugs may be formed by depositing an electromigration-inhibiting liner in the windows and then depositing electrically conductive material to fill the windows. Portions of either or both of the plugs and conductive segments are removed such that the plugs and conductive segments have a coplanar surface. The plugs may be formed in windows in an electrically conductive layer defining the conductive segments.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: January 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement, Bruce Gieseke
  • Patent number: 6245996
    Abstract: An integrated circuit is formed having electrical conductors with electromigration-inhibiting/electrically conductive plugs disposed between electrically conductive segments of the electrical conductor. Windows are formed within a planar surface. An electromigration-inhibiting/electrically conductive material is deposited over the planar surface and through the windows to fill the windows and thereby provide, in such windows, plugs of electromigration-inhibiting/electrically conductive material. Portions of the electromigration-inhibiting/electrically conductive material are removed to form the plugs with surfaces co-planar a surface surrounding the plugs. The electrical conductive segments are formed within the same planar surface as the plugs, either before, or after, the plug formation. The electrical conductive segments have surfaces co-planar with the plugs, are aligned with and electrically interconnected through the plugs.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: June 12, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement, Bruce Gieseke
  • Publication number: 20010001427
    Abstract: A method is provided for forming integrated circuit electrical conductors with electromigration-inhibiting/electrically conductive plugs disposed between electrically conductive segments of the electrical conductor. In accordance with such method, windows are formed within a planar surface. An electromigration-inhibiting/electrically conductive material is deposited over the planar surface and through the windows to fill the windows and thereby provide, in such windows, plugs of electromigration-inhibiting/electrically conductive material. Portions of the electromigration-inhibiting/electrically conductive material are removed to form the plugs with surfaces co-planar a surface surrounding the plugs. The electrical conductive segments are formed within the same planar surface as the plugs, either before, or after the plug formation. The electrical conductive segments have surfaces co-planar with the plugs, are aligned with and electrically interconnected through the plugs.
    Type: Application
    Filed: December 12, 2000
    Publication date: May 24, 2001
    Inventors: Eugenia Atakov, Adam Shepela, Lawrence Bair, John Clement, Bruce Gieseke