Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.

Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.

Abstract: Various through silicon via capacitors and methods of fabricating the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor substrate with a portion doped with a first impurity type and a doped region of a second impurity type in the portion of the semiconductor substrate. The doped region is operable to function as a first capacitor plate. A first via hole is in the doped region. The first via hole has a first sidewall. A first insulating layer is on the first sidewall. The first insulating layer is operable to function as a capacitor dielectric. A first conductive via is in the first via hole. The first conductive via is operable to function as a second capacitor plate.