Patents by Inventor Lawrence A. Curtis
Lawrence A. Curtis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8914761Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: GrantFiled: May 6, 2013Date of Patent: December 16, 2014Assignee: Mentor Graphics CorporationInventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr.
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Publication number: 20130246985Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Mentor Graphics CorporationInventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, JR.
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Patent number: 8438516Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: GrantFiled: May 4, 2010Date of Patent: May 7, 2013Assignee: Mentor Graphics CorporationInventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr.
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Publication number: 20100287524Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: ApplicationFiled: May 4, 2010Publication date: November 11, 2010Inventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, JR.
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Patent number: 7712062Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: GrantFiled: February 11, 2008Date of Patent: May 4, 2010Inventors: Tai An Ly, Ka Kie Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr.
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Patent number: 7478028Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.Type: GrantFiled: January 12, 2005Date of Patent: January 13, 2009Inventors: Chian-Min Richard Ho, Robert Kristianto Mardjuki, David Lansing Dill, Jing Chyuarn Lin, Ping Fai Yeung, Paul II Estrada, Jean-Charles Giomi, Tai An Ly, Kalyana C. Mulam, Lawrence Curtis Widdoes, Jr., Paul Andrew Wilcox
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Patent number: 7454728Abstract: During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.Type: GrantFiled: June 7, 2007Date of Patent: November 18, 2008Inventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Ross Andrew Andersen, Ping Fai Yeung, Neil Patrick Hand, Lawrence Curtis Widdoes, Jr.
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Publication number: 20080134115Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: ApplicationFiled: February 11, 2008Publication date: June 5, 2008Applicant: MENTOR GRAPHICS CORPORATIONInventors: Tai An Ly, Ka Kie Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes
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Patent number: 7356789Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.Type: GrantFiled: May 27, 2005Date of Patent: April 8, 2008Inventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Lawrence Curtis Widdoes, Jr.
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Patent number: 7243322Abstract: During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.Type: GrantFiled: June 1, 2004Date of Patent: July 10, 2007Inventors: Tai An Ly, Ka Kei Kwok, Vijaya Vardhan Gupta, Ross Andrew Ander, Ping Fai Yeung, Neil Patrick Hand, Lawrence Curtis Widdoes, Jr.
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Patent number: 7007249Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.Type: GrantFiled: January 20, 2003Date of Patent: February 28, 2006Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul II Estrada, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Jr., Ping Fai Yeung
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Patent number: 6885983Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.Type: GrantFiled: May 4, 2001Date of Patent: April 26, 2005Assignee: Mentor Graphics CorporationInventors: Chian-Min Richard Ho, Robert Kristianto Mardjuki, David Lansing Dill, Jing Chyuarn Lin, Ping Fai Yeung, Paul Il Estrada, Jean-Charles Giomi, Tai An Ly, Kalyana C. Mulam, Lawrence Curtis Widdoes, Jr., Paul Andrew Wilcox
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Publication number: 20030200515Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.Type: ApplicationFiled: January 20, 2003Publication date: October 23, 2003Applicant: 0-In Design automation Inc.Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Ii Estrada, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Ping Fai Yeung
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Patent number: 6609229Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior.Type: GrantFiled: August 9, 2000Date of Patent: August 19, 2003Assignee: O-In Design Automation, Inc.Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Estrada, II, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Jr., Ping Fai Yeung
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Publication number: 20020169027Abstract: A golf hole for a miniature golf course is formed of a plurality of components, these components being divided into three distinct types: platform base panels, side rails, and riser feet. Each platform base panel is constructed or molded with attachments for side rails and riser feet. The riser feet are first attached to platform base panels. The platform base panels are laid out in any desired hole configuration within the parameters of the invention, one platform base panel containing the golf cup. Carpet or artificial turf, continuous or in sections, is then cut to fit and laid over platform base panels. The side rails and metal start rails are placed over the edge of the carpet along the perimeter of the hole and secured to the platform base panels. Obstacles may be bolted to the platform base panels at various points on the putting surface.Type: ApplicationFiled: May 11, 2002Publication date: November 14, 2002Inventor: Lawrence Curtis Fowler
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Patent number: 6469776Abstract: A method is provided for transferring dye from a dye imbibed matrix film to a receiver film for producing a dye transfer print of a motion picture print. A dye imbibed matrix film and a receiver film are superimposed together in precise registration on a seating apparatus, e.g., a pin belt, to create a two-film sandwich. The two-film sandwich is stripped from the seating apparatus before completing dye transfer, and dye transfer from the matrix film to the receiver film is completed along a pinless, substantially rectilinear film path while maintaining the two-film sandwich in precise registration. For example, a transfer cabinet may be provided that includes a plurality of rollers having a predetermined relationship to one another and defining the substantially rectilinear film path, and the two-film sandwich may be directed along the film path to complete dye transfer.Type: GrantFiled: June 15, 2001Date of Patent: October 22, 2002Assignee: Technicolor, Inc.Inventors: Ronald W. Jarvis, Richard J. Goldberg, Frank J. Ricotta, Ronald W. Corke, Lawrence A. Curtis, Steven Garlick, David M. Gilmartin
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Publication number: 20020018196Abstract: A system for producing prints of a professional motion picture film by dye transfer, including a roll tank, a pin belt, and a transfer cabinet. A dye imbibed matrix film and blank film are superimposed together in a predetermined registration by rollers in the roll tank, creating a two-film sandwich, which is directed onto the pin belt. The pin belt includes a plurality of pins traveling in an orbital path, which detachably engage the two-film sandwich, thereby directing the two-film sandwich along a portion of the orbital path. The transfer cabinet includes a plurality of relatively large diameter rollers in a predetermined relationship to one another, and an elevator mechanism for adjusting the predetermined relationship. The rollers define a substantially rectilinear film path along which the two-film sandwich from the pin belt is directed. The film path has a length sufficient to allow complete dye transfer to occur at high drive speeds within the transfer cabinet.Type: ApplicationFiled: June 15, 2001Publication date: February 14, 2002Applicant: Technicolor, Inc.Inventors: Ronald W. Jarvis, Richard J. Goldberg, Frank J. Ricotta, Ronald W. Corke, Lawrence A. Curtis, Steven Garlick, David M. Gilmartin
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Patent number: 6327027Abstract: A system for producing prints of a professional motion picture film by dye transfer, including a roll tank, a pin belt, and a transfer cabinet. A dye imbibed matrix film and blank film are superimposed together in a predetermined registration by rollers in the roll tank, creating a two-film sandwich, which is directed onto the pin belt. The pin belt includes a plurality of pins traveling in an orbital path, which detachably engage the two-film sandwich, thereby directing the two-film sandwich along a portion of the orbital path. The transfer cabinet includes a plurality of relatively large diameter rollers in a predetermined relationship to one another, and an elevator mechanism for adjusting the predetermined relationship. The rollers define a substantially rectilinear film path along which the two-film sandwich from the pin belt is directed. The film path has a length sufficient to allow complete dye transfer to occur at high drive speeds within the transfer cabinet.Type: GrantFiled: July 24, 2000Date of Patent: December 4, 2001Assignee: Technicolor, Inc.Inventors: Ronald W. Jarvis, Richard J. Goldberg, Frank J. Ricotta, Ronald W. Corke, Lawrence A. Curtis, Steven Garlick, David M. Gilmartin
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Patent number: 6292765Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.Type: GrantFiled: October 20, 1997Date of Patent: September 18, 2001Assignee: O-In Design AutomationInventors: Chian-Min Richard Ho, Robert Kristianto Mardjuki, David Lansing Dill, Jing Chyuarn Lin, Ping Fai Yeung, Paul II Estrada, Jean-Charles Giomi, Tai An Ly, Kalyana C. Mulam, Lawrence Curtis Widdoes, Jr., Paul Andrew Wilcox
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Patent number: 6175946Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.Type: GrantFiled: October 20, 1997Date of Patent: January 16, 2001Assignee: O-IN Design AutomationInventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Estrada, II, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Jr., Ping Fai Yeung