Patents by Inventor Lawrence A. Rigge
Lawrence A. Rigge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8374661Abstract: In one embodiment, an apparatus comprising a housing and a fastener, such as a clip (101, 201) for fastening the apparatus (100, 200) to an article of clothing. The housing (102, 202) has a recess (103, 203) formed therein, such that at least a portion of the fastener is adapted to fit within the recess. The fastener is adapted to travel slidably within the recess (103, 203) between a first position in which the fastener enables the apparatus (100, 200) to be fastened to an external object and a second position in which the fastener is stowed away.Type: GrantFiled: December 18, 2007Date of Patent: February 12, 2013Assignee: Agere Systems LLCInventors: Roger A. Fratti, Douglas D. Lopata, Lawrence A. Rigge
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Publication number: 20120239719Abstract: Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.Type: ApplicationFiled: June 4, 2012Publication date: September 20, 2012Applicant: AGERE SYSTEMS INC.Inventor: Lawrence A. Rigge
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Patent number: 8214416Abstract: Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.Type: GrantFiled: July 28, 2008Date of Patent: July 3, 2012Assignee: Agere Systems Inc.Inventor: Lawrence A. Rigge
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Publication number: 20100267431Abstract: In one embodiment, an apparatus comprising a housing and a fastener, such as a clip (101, 201) for fastening the apparatus (100, 200) to an article of clothing. The housing (102, 202) has a recess (103, 203) formed therein, such that at least a portion of the fastener is adapted to fit within the recess. The fastener is adapted to travel slidably within the recess (103, 203) between a first position in which the fastener enables the apparatus (100, 200) to be fastened to an external object and a second position in which the fastener is stowed away.Type: ApplicationFiled: December 18, 2007Publication date: October 21, 2010Applicant: AGERE SYSTEMS INC.Inventors: Roger A. Fratti, Douglas Lopata, Lawrence A. Rigge
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Publication number: 20100023574Abstract: Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.Type: ApplicationFiled: July 28, 2008Publication date: January 28, 2010Applicant: AGERE SYSTEMS INC.Inventor: Lawrence A. Rigge
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Patent number: 7382189Abstract: In one embodiment, an amplifier circuit has at least one branch and current-source circuitry providing a tail current to the branch, which has at least one load tank, at least one input transistor coupled to the load tank, and variable-impedance circuitry coupled between an input node of the amplifier circuit and the gate of the input transistor. The transconductance of the input transistor can be altered to achieve two or more different gain settings for the amplifier circuit. The variable-impedance circuitry can be controlled to contribute any one of at least two different levels of impedance to the overall input impedance of the amplifier circuit. If the transconductance of the input transistor is reduced, then the variable-impedance circuitry can increase the level of impedance contributed to the overall input impedance of the amplifier circuit such that the overall input impedance of the amplifier circuit remains substantially unchanged.Type: GrantFiled: September 25, 2006Date of Patent: June 3, 2008Assignee: Agere Systems Inc.Inventors: Jinghong Chen, Shaorui Li, Lawrence A. Rigge
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Publication number: 20080074187Abstract: In one embodiment, an amplifier circuit has at least one branch and current-source circuitry providing a tail current to the branch, which has at least one load tank, at least one input transistor coupled to the load tank, and variable-impedance circuitry coupled between an input node of the amplifier circuit and the gate of the input transistor. The transconductance of the input transistor can be altered to achieve two or more different gain settings for the amplifier circuit. The variable-impedance circuitry can be controlled to contribute any one of at least two different levels of impedance to the overall input impedance of the amplifier circuit. If the transconductance of the input transistor is reduced, then the variable-impedance circuitry can increase the level of impedance contributed to the overall input impedance of the amplifier circuit such that the overall input impedance of the amplifier circuit remains substantially unchanged.Type: ApplicationFiled: September 25, 2006Publication date: March 27, 2008Inventors: Jinghong Chen, Shaorui Li, Lawrence A. Rigge
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Patent number: 7162212Abstract: A system for, and method of, obscuring ambient noise. In one embodiment, the system includes: (1) a background sound generator, (2) a mixer coupled to the background sound generator and (3) a user interface, coupled to the mixer, that, upon a user command, causes the mixer to mix an output of the background sound generator with a transmitted signal. The background sound may be music, white noise, colored noise, out-of-phase ambient noise, simulated alternative ambient noise or any other suitable background sound. The system may be associated with a wireless handset, a wireline handset, central office equipment or any other suitable location or equipment.Type: GrantFiled: September 22, 2003Date of Patent: January 9, 2007Assignee: Agere Systems Inc.Inventors: David J. Bennetts, Lawrence A. Rigge, Richard P. Verney
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Patent number: 6985718Abstract: A charge meter system and method of compiling utilization fees associated with a data transmission in a packet switched communications network. In one embodiment, the charge meter system includes a counter that counts a number of data packets associated with the data transmission and a charge rate subsystem that obtains a charge rate associated with the data transmission. The charge meter system also includes a calculation subsystem that calculates utilization fees based on the number of data packets and the charge rate of the data transmission. The charge meter system further includes an indication subsystem that provides the utilization fees to a user via user equipment participating in the data transmission.Type: GrantFiled: June 19, 2003Date of Patent: January 10, 2006Assignee: Agere Systems Inc.Inventors: Norman Goris, Lawrence A. Rigge, Wolfgang Scheit
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Publication number: 20040259526Abstract: A charge meter system and method of compiling utilization fees associated with a data transmission in a packet switched communications network. In one embodiment, the charge meter system includes a counter that counts a number of data packets associated with the data transmission and a charge rate subsystem that obtains a charge rate associated with the data transmission. The charge meter system also includes a calculation subsystem that calculates utilization fees based on the number of data packets and the charge rate of the data transmission. The charge meter system further includes an indication subsystem that provides the utilization fees to a user via user equipment participating in the data transmission.Type: ApplicationFiled: June 19, 2003Publication date: December 23, 2004Applicant: Agere Systems Inc.Inventors: Norman Goris, Lawrence A. Rigge, Wolfgang Scheit