Abstract: In one embodiment, a method displays images from a remote desktop of a desktop GUI on a client device. The method receives a plurality of image blocks for a frame update of an image of the desktop GUI being displayed on the client device. The remote desktop is being run on a host. The client device determines that one or more missing image blocks have not been received for the frame update and determines if the frame update should be performed without the one or more missing image blocks. If the frame update of the desktop GUI should be performed without the one or more missing image blocks, the client device performs the frame update of the desktop GUI using the plurality of image blocks without using the one or more missing image blocks.

Abstract: In one embodiment, a client device configured to remotely access a desktop hosted by a server system determines an event related to a user input for a desktop operation directed to the desktop. The client device receives a plurality of updates to a desktop graphical user interface (GUI) from the desktop hosted by the server system. Then, the client device correlates the event to an update in the plurality of updates to the desktop GUI based on a rule in a set of rules correlating events to updates. A metric is monitored for the update and information measured for the metric is stored.

Abstract: In one embodiment, a server system receives, from a client device configured to remotely access a desktop hosted by the server system, user input directed to the desktop. The server system further identifies a desktop operation to be performed in response to the user input, where the identifying is performed without relying on preconfigured information that indicates what the desktop operation should be, determines when the desktop operation has completed, and adds, upon completion of the desktop operation, one or more markers to the desktop. The server system then transmits an image of the desktop that includes the one or more markers to the client device, thereby signaling the completion of the desktop operation to the client device.

Abstract: The disclosure herein describes a client-side system that enhances user experience on a remoting client without consuming additional network bandwidth. During operation, the system receives a sequence of frame updates for a display screen, and determines a sequence of frames corresponding to the frame updates. The system further adaptively applies one or more image enhancing techniques to the sequence of frames based on available network bandwidth, frame refresh rate, or image quality. The image enhancement techniques include predicting a frame based on previously received frames, interpolating a frame based on at least two buffered frames, and reducing appearance of artifacts in a received frame, thereby reducing visual artifacts.

Abstract: A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under the control of the hypervisor. Each domain is allocated memory resources that include accessible memory space that is exclusively accessible by that domain. Each domain is allocated one or more processor resources. The hypervisor identifies domain layout information that includes a boundary of accessible memory space of each domain. The hypervisor provides the domain layout information to each processor resource. Each processor resource is configured to implement, on a per domain basis, a restricted coherency protocol based on the domain layout information. The restricted coherency protocol bypasses, relative to the domain, downstream caches when a cache line falls within the accessible memory space of that domain.

Abstract: A method and processor supporting architected instructions for tracking and determining set membership, such as by implementing Bloom filters are disclosed. The apparatus includes storage arrays (e.g., registers) and an execution core configured to store an indication that a given value is a member of a set, including by executing an architected instruction having an operand specifying the given value, wherein executing comprises applying a hash function to the value to determine an index into one of the storage arrays and setting a bit of the storage array corresponding to the index. An architected query instruction is later executed to determine if a query value is not a member of the set, including by applying the hash function to the query value to determine an index into the storage array and determining whether a bit at the index of the storage array is set.

Abstract: Image data representing a desktop image for a client device that is accessing the desktop remotely is compressed according to a method that preserves image fidelity in selected non-text regions. The method, which is carried out in a remote server, includes the steps of generating image data for the remote desktop image and analyzing different regions of the remote desktop image, identifying those regions of the remote desktop image that are text regions, selecting non-text regions of the remote desktop image for lossless compression based on a spatial relationship between the non-text regions and the text regions, compressing the image data using a lossless compression protocol for a portion of the image data corresponding to the selected non-text regions, and transmitting the compressed image data to the client device.

Abstract: Systems and methods for performing single instruction multiple data (SIMD) operations on a data set. The methods may include examining a structure of the data set to determine what reorganization may be necessary to facilitate SIMD processing. The method may include selecting a stored bit mask corresponding to the organization of the data set and loading the bit mask into an application specific register (ASR). Subsequently, the data may be reorganized inline according to the ASR as the data is loaded into the SIMD functional unit such that the SIMD functional unit may operate on the data set. The results of the SIMD operation may be written to a results register.

Abstract: In one embodiment, a method displays images from a remote desktop of a desktop GUI on a client device. The method receives a plurality of image blocks for a frame update of an image of the desktop GUI being displayed on the client device. The remote desktop is being run on a host. The client device determines that one or more missing image blocks have not been received for the frame update and determines if the frame update should be performed without the one or more missing image blocks. If the frame update of the desktop GUI should be performed without the one or more missing image blocks, the client device performs the frame update of the desktop GUI using the plurality of image blocks without using the one or more missing image blocks.

Abstract: A processor including instruction support for implementing the Data Encryption Standard (DES) block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more DES instructions defined within the ISA. In addition, the DES instructions may be executable by the cryptographic unit to implement portions of an DES cipher that is compliant with Federal Information Processing Standards Publication 46-3 (FIPS 46-3). In response to receiving a DES key expansion instruction defined within the ISA, the cryptographic unit may generate one or more expanded cipher keys of the DES cipher key schedule from an input key.

Abstract: A computer-implemented method for creating a social network of members of a virtualization infrastructure. At a virtualization infrastructure manager, at least a portion of the members of the virtualization infrastructure are identified. Parent/child relationships of identified members of the virtualization infrastructure are identified. A social network of the identified members of the virtualization infrastructure is generated based on the parent/child relationships. Affiliation relationships between parent members and child members of the virtualization infrastructure are established, wherein the child members can access shared message streams corresponding to the parent members, such that a child member can establish an association of a message with an indication that the child member identifies with content of the message.

Abstract: A computer-implemented method to facilitate administration of a network of members. Members of a network are provided with access to a shared message stream such that the members of the network are able to monitor messages generated by other members of the network posted to the shared message stream, wherein at least some of the messages are indicative of operational conditions of particular other members which generated the messages. Responsive to a first member of the network identifying a specific operational condition of the first member, the shared message stream is monitored for a message related to the specific operational condition. Provided the shared message stream includes a message related to the specific operational condition identified by the first member, an association of the message with an indication that the first member identifies with the specific operational condition is established, wherein the first member is configured to establish the association.

Abstract: Techniques are disclosed relating to a processor including instruction support for performing a Montgomery multiplication. The processor may issue, for execution, programmer-selectable instruction from a defined instruction set architecture (ISA). The processor may include an instruction execution unit configured to receive instructions including a first instance of a Montgomery-multiply instruction defined within the ISA. The Montgomery-multiply instruction is executable by the processor to operate on at least operands A, B, and N residing in respective portions of a general-purpose register file of the processor, where at least one of operands A, B, N spans at least two registers of general-purpose register file. The instruction execution unit is configured to calculate P mod N in response to receiving the first instance of the Montgomery-multiply instruction, where P is the product of at least operand A, operand B, and R^?1.

Abstract: Improved performance of a chip multithreading (CMT) processor during processing of a cipher is disclosed. The chip multithreading processor may be located on a chip multithreading processor chip that includes a processor cache. The selection of a cipher is received. The cipher is processed by executing a plurality of cryptographic operations on the chip multithreading processor. Lookup tables used during the execution of the plurality of cryptographic operations are determined. The size of at least one of the lookup tables may be increased, such that the at least one lookup table is able to be stored in a processor cache located on the chip multithreading processor chip. Further adjustments may be made to the size of one or more lookup tables depending on the cipher selected, other operations executing on the chip multithreading processor, or both.

Abstract: The generation of Fletcher/Alder partial checksums are transformed from a space that requires integer multiplications and additions to a space that requires only integer additions and shifts on a single SIMD pipeline capable processor. This transformation permits the use of Fletcher/Alder checksums on processors where the performance of SIMD instructions are sub-optimal, on CMT processors that support a single SIMD pipeline as well as other processors that can be configured by executing software to implement SIMD operations for a single SIMD pipeline. The implementation of the process with this transformation on a general-purpose computer system transforms that general-purpose computer system into a special-purpose computer system that uses a single SIMD pipeline to generate a Fletcher/Alder checksum. The elimination of integer multiplications in the generation of the partial checksums results in a significant improvement in performance.

Abstract: Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, where the first instance of the CRC instruction is executable by the cryptographic unit to perform a first CRC operation on a set of data that produces a checksum value. In one embodiment, the cryptographic unit is configured to generate the checksum value using a generator polynomial of 0x11EDC6F41.

Abstract: In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.

Abstract: In response to executing a single arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is added implicitly to generate a result that represents the first number multiplied by the second number summed with the partial result from a previously executed single arithmetic instruction. The high order portion of the generated result is saved in an extended carry register as a next partial result for use with execution of a subsequent single arithmetic instruction. Execution of a single arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number.

Abstract: Systems and methods for efficient instruction support of an multiple features for opcodes of an instruction set. A processor detects a fetched instruction of a computer program comprises an opcode corresponding to a plurality of functions. Each function corresponds to a different type of operation. The processor determines the received instruction corresponds to a feature requested by the computer program, such as a cryptographic algorithm. A determination is made as to whether hardware support exists for the feature. If hardware support exists for the feature, the instruction is executed on-chip by the hardware. Otherwise, software performs the operation corresponding to the instruction.

Abstract: The generation of Fletcher/Alder partial checksums are transformed from a space that requires integer multiplications and additions to a space that requires only integer additions and shifts on a single SIMD pipeline capable processor. This transformation permits the use of Fletcher/Alder checksums on processors where the performance of SIMD instructions are sub-optimal, on CMT processors that support a single SIMD pipeline as well as other processors that can be configured by executing software to implement SIMD operations for a single SIMD pipeline. The implementation of the process with this transformation on a general-purpose computer system transforms that general-purpose computer system into a special-purpose computer system that uses a single SIMD pipeline to generate a Fletcher/Alder checksum. The elimination of integer multiplications in the generation of the partial checksums results in a significant improvement in performance.