Abstract: A system and method for transmitting parallel data from a source to a destination over a plurality of high speed serial lines operates reliably even in the presence of data skew. The high speed data transmission system includes a protocol generator, a de-skew circuit, and a plurality of high speed serial lines coupled between the protocol generator and the de-skew circuit. Respective serial representations of parallel data words are transmitted to the destination over a plurality of serial data lines, and a clock signal is transmitted to the destination over a clock line in parallel with the serial data lines. The clock signal has at least one data bit of each parallel data word encoded thereon. The de-skew circuit aligns regenerated parallel data words using the respective data bits encoded on the clock signal to eliminate skew among the data bits, and regenerates the parallel data from the aligned parallel data words.

Abstract: Flow of data units to an address resolution processor is controlled to inhibit multiple data units from a single multicast flow from being enqueued with the address resolution processor. In a switch having a plurality of Input/Output Application Specific Integrated Circuits (“I/O ASICs”) with a plurality of ports, no more than one data unit from each I/O ASIC is permitted to be enqueued with the address resolution processor at any point in time. A separate learn pending indicator may be defined for each I/O ASIC in the switch.