Abstract: Techniques are disclosed for automatic generation of a location-indicative instruction displayable to one or more users in a communication system which includes a wireless network comprising a plurality of user devices adapted for communication with at least one access point device. A test of a communication link between at least one of the user devices and the access point device is initiated. Based at least in part on a result of the test, an instruction displayable to a user associated with a given one of the user devices is generated, the instruction being indicative of a location at which the given user device is expected to obtain a particular level of data throughput performance.

Abstract: A method and apparatus are provided for wireless communication between an integrated circuit device and a monitoring station. Each integrated circuit device has one or more antennas that permit wireless communication with an external monitoring station. A signal destined for an integrated circuit device is transmitted by the monitoring station using an associated antenna. An antenna associated with the destination integrated circuit receives the transmitted signal. The antenna(s) may be embodied, for example, as pins that are external to the integrated circuit device, or printed or etched on the integrated circuit device itself. Greater bandwidth can be achieved, if necessary, by pooling the bandwidth of several antennas.

Abstract: There is disclosed an input device including a display for displaying a plurality of icons, and a selector for selecting a displayed icon. At least a portion of the display is an electronic display. The device is adapted such that the selector moves relative to the display between a plurality of positions. At least one position corresponds to a displayed icon. The device further includes a function selection means. A function associated with an icon corresponding to a current position of the selector is selected when the function selection means is enabled.

Abstract: An application-specific single chip digital processor having flexible design expansion capability with minimal impact on the performance of a processor core. The processor core has an ALU and a register file (accumulators). The output of the ALU is connected to a multiplexer whose output is connected to the input of the register file. The output of the register file connects to one input of the ALU. A function unit, separate from the core, has an input connected to the output of the register file and an output connected to another input to the multiplexer. The core operates with a predefined instruction set. The function unit, which may be redesigned depending on the application, operates with a reserved (uncommitted) instruction set under control of the core.

Abstract: An application-specific single chip digital processor having flexible design expansion capability with minimal impact on the performance of a processor core. The processor core has an ALU and a register file (accumulators). The output of the ALU is connected to a multiplexer whose output is connected to the input of the register file. The output of the register file connects to one input of the ALU. A function unit, separate from the core, has an input connected to the output of the register file and an output connected to another input to the multiplexer. The core operates with a predefined instruction set. The function unit, which may be redesigned depending on the application, operates with a reserved (uncommitted) instruction set under control of the core.