Abstract: An example method is performed at a device with a display and a biometric sensor. While the device is in a locked state, the method includes displaying a log-in user interface that is associated with logging in to a first and second user account. While displaying the log-in user interface, the method includes, receiving biometric information, and in response to receiving the biometric information: when the biometric information is consistent with biometric information for the first user account and the first user account does not have an active session, displaying a prompt to input a log-in credential for the first user account; and when the biometric information is consistent with biometric information for the second user account and the second user account does not have an active session on the device, displaying a prompt to input a log-in credential for the second user account.

Abstract: An example method is performed at a device with a display and a biometric sensor. While the device is in a locked state, the method includes displaying a log-in user interface that is associated with logging in to a first and second user account. While displaying the log-in user interface, the method includes, receiving biometric information, and in response to receiving the biometric information: when the biometric information is consistent with biometric information for the first user account and the first user account does not have an active session, displaying a prompt to input a log-in credential for the first user account; and when the biometric information is consistent with biometric information for the second user account and the second user account does not have an active session on the device, displaying a prompt to input a log-in credential for the second user account.

Abstract: A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. The method additionally includes a procedure for minimizing wire lengths in the compacted layout. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. To adjust a circuit layout, the cells in the layout are processed in a sorted order.

Abstract: A computer-aided design system for compacting an integrated circuit layout with standard cell components is described. A data receiving device is used to process an integrated circuit layout that includes standard cell components. The integrated circuit layout is characterized by a circuit layout database with a cell table defining a set of cells that represent all spaces in the integrated circuit layout. The cell table includes connector cell data to indicate whether a cell forms a portion of a connected group of cells. The system includes an adjustment mechanism to align internal connectors of a standard cell with a routing grid associated with the integrated circuit layout. The system also includes a movement mechanism to position right-edge external connectors of a standard cell at a uniform routing grid coordinate position. The system uses the connector cell data to identify a power bus and a ground bus of each standard cell.

Abstract: A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented in the database. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. However, the method sizes gate cells of transistors differently from other cells by maintaining the former at predetermined dimensions, with a user-definable override to resize transistors to a percentage of the predetermined dimensions.

Abstract: A method an apparatus for generating and storing a connectivity data structure representing a circuit layout. The data structure includes a list of pointers representing cells of the layout, and each cell pointer points to an entry in a cell table. The cell table entries include a field pointing to a cell types table, and another entry pointing to a boundary table, which itself stores fields identifying edges and adjacent cells. The edge entries point to an edge table including fields representing the endpoints of the edge. The endpoint fields point to a point table including coordinates of the endpoint in question and a move field identifying whether the edge has been moved in a layout modification routine. The method of generating this data structure involves entering a layout, adding new cells one by one, and when each new cell is added, generating entries for all the cells, boundaries, edges and edge endpoints of the new cell, and storing them in the data structure.

Abstract: A computer aided design process for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a maximal set of trapezoids and storing the resulting trapezoidal cells in a database that denotes the boundaries of each cell, and the cell adjacent to each boundary. Empty spaces between cells are represented by additional cells. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When an edge of a cell is moved, the shared edge of each neighboring cell is implicitly moved because it uses the same edge data. To adjust a circuit layout, the cells in the layout are processed in sorted order. For each cell, a set of width and spacing design rules are applied to the bottom and top edges of the cell which may result in movement of the cell and adjustment of the cell's width.