Abstract: A system generally relating to an SoC, which may be a field programmable SoC (“FPSoC”), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.

Abstract: A method relating generally to loading a boot image is disclosed. In such a method, a header of a boot image file is read by boot code executed by a system-on-chip. It is determined whether the header read has an authentication certificate. If the header has the authentication certificate, authenticity of the header is verified with the first authentication certificate. It is determined whether the header is encrypted. If the header is encrypted, the header is decrypted.

Abstract: A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBS) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The state data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.

Abstract: A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBs) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that-results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The user data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.

Abstract: A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

Abstract: An integrated circuit receives an external clock signal and generates therefrom a clock signal that is supplied to a plurality of external devices. A delay-locked loop (DLL), a balanced clock tree, and a plurality of interface cells on the integrated circuit function together to supply the clock signal to the plurality of external devices such that the clock signal at each of the external devices is deskewed with respect to the external clock signal. Board level design is simplified because no balanced clock tree is needed to route the clock signal from the integrated circuit to the external devices, rather each external device is coupled to a corresponding one of the interface cells via a separate external connection. Each of these external connections has an equal propagation delay. One of the interface cells supplies the clock signal back to a reference signal input of the DLL via an external connection.

Abstract: A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

Abstract: An FPGA configuration circuit including a mask register that stores mask data during configuration memory read-modify-write operations. The mask data enables a multiplexing circuit to overwrite selected memory cells in a configuration memory array with new data bit values. Data bit values from all other memory cells in the configuration memory array are fed back by the multiplexing circuit. In one embodiment, the new data bit values are transmitted on a bi-directional bus and stored in a shift register. The configuration memory array is arranged in frames that are addressed by a frame address register, and the contents of an addressed frame are written to a shadow register. Under the control of the mask register, the multiplexing circuit modifies the frame data bit values stored in the shadow register using the new data bit values stored in the shift register. The contents of the shadow register are then written into the addressed frame.

Abstract: An FPGA configuration circuit including a bus interface for applying a bit stream from either a JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses a header word from the bit stream into an address field and an operand field. Several registers are connected to the bus including a frame data register, a frame address register, a control register, a command register, and an optional data check register. The bus interface generates control signals in response to the address field and the operand field that cause one or more registers to perform predefined operations according to subsequent data words in the bit stream. For example, during configuration write operations, the bus interface enables the frame data register to receive data signals that are subsequently transferred to a configuration memory array.

Abstract: A cyclic redundancy check (CRC) register is connected to the bi-directional bus and a packet processor in a configuration circuit of an FPGA. The CRC register performs transmission error detection functions based on the command/data transmissions to various registers connected to the bus, and based on the address information transmitted from the packet processor to an address/operand decoder used to enable the various registers to receive subsequent command/data words. The CRC register calculates a check-sum value in accordance with a predetermined equation. At any time during the transmission (e.g., halfway through configuration or at the end of configuration), a pre-calculated check-sum value is transmitted to the CRC register that represents an expected check-sum value at the selected time. The pre-calculated check-sum value is then compared with the check-sum value currently stored in the CRC register.

Abstract: A programmable logic device (PLD), such as a field-programmable gate array (FPGA), includes an integrated delay-locked loop that produces a lock signal internal to the FPGA. The FPGA also includes a sequencer and related global signals adapted to configure the FPGA using external configuration data. The sequencer disables the FPGA during the configuration process. The sequencer then continues to disable the fully configured FPGA until receipt of the lock signal. The configuration process, including the establishment of a valid internal clock, is controlled entirely within the FPGA. In one embodiment, an FPGA can be fully or partially reconfigured without powering down the device. The delay-locked loop maintains a lock on the clock signal so that the sequencer need not wait for the lock signal after reconfiguration.

Abstract: A field programmable gate array having memory cells that can be partially reconfigured comprises an array of tiles having logic blocks and routing structures, an array of associated memory cells, a data register, an address register and a memory configuration device. The data register is coupled to store data in the memory cells, and the address register is coupled to address the memory cells by column. The memory configuration device preferably comprises a register, a decoder and a control unit for receiving a bit stream including a skip command or a write command plus data. The memory configuration device allows the memory cells to be partially reconfigured by allowing each column of memory cells to be selectively written or skipped in response to the command inserted into the bit stream.

Abstract: A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells. The control unit then generates an address signal to transfer the column of data held in the plurality of shift registers into the memory cells.