Abstract: A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.

Abstract: In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

Abstract: A semiconductor device disables itself during power-up until the internal power supply voltage and other circuits reach states in which the device can operate properly. The internal power supply voltage is coupled to the input terminal of an inverter through a delay network. During power-up, the device remains disabled until the voltage at the input terminal of the inverter reaches the inverter trip point. The delay network and the inverter are designed so that the voltage at the inverter's input terminal does not reach the inverter trip point until the internal power supply voltage and other circuits have reached states in which the device can operate properly. When the (device is turned off, the inverter input terminal is discharged quickly by a diode or resistor. Therefore, if the power is turned back on immediately, a suitable delay will be provided.

Abstract: A compact laser programmable fuse structure has a central line and two sets of fuses extending from opposite sides of the central line. An opening through a passivation layer exposes the fuses and overlies the central line. In one embodiment, the opening also exposes the portions of the central line. The central line is made of fuse material or another material for which the opening does not create reliability problems. In one embodiment of the invention, the central line and the fuses are parts of a single contiguous region of polysilicon. This fuse structure has a length that is about half the length of conventional fuse structure having the same number of fuses because two fuses, one on either side of the central line, fit within a length used for a single fuse in conventional fuse structures.

Abstract: A long X bit or a long Y bit is stored in a latch and used to supplement the Y address bits in an asymmetric DRAM memory thereby to allow one part to be used for a design requiring a long X bit and also for a design requiring a long Y bit.

Abstract: An integrated circuit has a supply node for supplying power to at least one intermediate node coupled to circuitry for receiving power. Rather than transmit power from the supply node to the intermediate node by means of a power bus formed as part of the chip interconnect structure, power is supplied to an external wire which is coupled from the supply to the intermediate node. Other than as connected to the supply node and intermediate node, the wire is electrically isolated from the die.This structure and method for making the semiconductor package allow power to be distributed within a semiconductor chip without sacrificing valuable chip space and without requiring a special lead frame for distributing the power within the semiconductor chip.

Abstract: The voltages on the high voltage rails of sense amplifiers in dynamic random access memories are controlled during turn-on of the sense amplifiers to remain approximately at the voltage of the voltage source internal to the integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltages on the rails equal the voltage from the chip's internal voltage source at which time the external voltage source is disconnected.

Abstract: In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

Abstract: A DRAM has a sensing circuit which includes an on-chip capacitors having a total capacitance greater than about 35% of the total capacitance of the bit lines. The on-chip capacitors are coupled to a power line of the sense amplifiers and stabilizes a power supply voltage to prevent voltage drop and noise during the large sensing currents for a read/refresh cycle. A read/refresh cycle in accordance with an embodiment of the invention includes precharging bit lines and the on-chip capacitors before connecting memory transistors to the bit lines and connecting power to the sense amplifiers. Capacitors can be formed in any available space in the integrated circuit particularly in space under metal bus lines in peripheral circuitry surrounding a memory array.

Abstract: A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.