Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

Abstract: An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.

Abstract: Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.

Abstract: Methods for fabricating a semiconductor device are provided. The method can include forming a conductive material layer on a semiconductor device, the semiconductor device including at least two gate structures and at least two source/drain surfaces of at least two source/drain regions, wherein an interlevel dielectric layer separates each of the at least two gate structures from each of the at least two source/drain surfaces, wherein the conductive material layer extends through openings of the interlevel dielectric layer, contacting the at least two source/drain surfaces and forming at least two conductive material interconnects, and wherein the conductive material layer extends over the interlevel dielectric layer, forming an interconnect mask over portions of the conductive material layer, wherein the conductive material layer includes an up-via and forming an interconnect by subtractively etching a portion of the conductive material layer, exposed through the interconnect mask.

Abstract: A semiconductor structure includes a field effect transistor (FET) including a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region under the gate and between the first and second source-drain regions. Also included are a front side wiring network, having a plurality of front side wires, on a front side of the field effect transistor; a front side conductive path electrically interconnecting one of the front side wires with the first source-drain region; a back side power rail, on a back side of the FET; and a back side contact electrically interconnecting the back side power rail with the second source-drain region. A dielectric liner and back side dielectric fill are on a back side of the gate adjacent the back side contact, and they electrically confine the back side contact in a cross-gate direction.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for optimizing clustering outputs. The method includes receiving data collected from a plurality of respondents. The method also includes grouping the plurality of respondents to a plurality of response groups based on a plurality of factors. The method also includes calculating, for each question of the plurality of questions, a fractional breakdown of each response group based at least in part on each response to each question. The method also includes calculating, for each response group of the plurality of response groups, a plurality of fractional groupings based at least in part on a grouping map. The method also includes selecting, for each response group of the plurality of response groups, a fractional grouping from the plurality of fractional groupings that satisfies a predefined criteria. The method also includes outputting the selected fractional groupings.

Abstract: A work glove (1,100,1000) for magnetically attracting and retaining one or more work items, the work glove (1,100,1000) comprising: a glove body configured to receive a wearer's hand in use, the glove body having a back surface (2,200,2000) arranged to overlie the back of the wearer's hand; and a multi-layered pouch (4,400,4000) attached to the back surface (2,200,2000) of the glove body, wherein the multi-layered pouch (4,400,4000) comprises: a magnetic layer (6,600,6000) composed of a magnetic material; a covering layer (5,500,5000) arranged to contact the one or more work items; and a plurality of magnets (8,800,8000) or ferromagnetic bodies located between the magnetic layer (6,600,6000) and the covering layer (5,500,5000), each of the magnets (8,800,8000) or ferromagnetic bodies being magnetically attached to the magnetic layer (6,600,6000) or ferromagnetic bodies layer, wherein the magnets (8,800,8000) are arranged in spaced relationship.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice has a time constant, and is controlled to switchably connect a driver output to either a high voltage level or a low voltage level, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. The circuit slices may also have programmable capacitors that may be adjusted to provide a programmable time domain behavior of the output voltage waveform, such as a programmable voltage peaking characteristic.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice has a time constant, and is controlled to switchably connect a driver output to either a high voltage level or a low voltage level, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. The circuit slices may also have programmable capacitors that may be adjusted to provide a programmable time domain behavior of the output voltage waveform, such as a programmable voltage peaking characteristic.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice is controlled to switchably connect a driver output to either a high voltage level or a low voltage level via a resistor, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. A calibration procedure is disclosed herein to generate a lookup table for how to selectively connect circuit slices to supply voltages given a target output voltage.

Abstract: A bandwidth adjustable transimpedance amplifier. The bandwidth adjustable transimpedance amplifier includes a feedback path with a selectable resistance. The bandwidth adjustable transimpedance amplifier is preferably implemented with a photodiode in a five pin package for an optical transceiver system, with a single pin providing a monitor out function and a rate select input.

Abstract: An automatic power control circuit for a laser driver includes precharge circuitry to precharge inputs to a comparator receiving an indication of laser output power, for example from a monitor photodiode. The precharge circuitry can be selectively activated when a laser driven by the laser driver is operating in burst mode, as opposed to operating in continuous mode. In addition, a digital up-down counter may be used to increase or decrease a digital value used to set a bias level for the laser, with the digital up-down counter counting up if the comparator indicates the laser output is too low and counting down if the comparator indicates the laser output is too high.

Abstract: A system and method for biasing the outputs of a laser modulator driver while allowing for high speed operation. A differential amplifier type modulator driver is provided which uses a reduced number of components in the high speed path. Additionally, the modulator driver may be constructed with a distributed output stage.

Abstract: A bandwidth adjustable transimpedance amplifier. The bandwidth adjustable transimpedance amplifier includes a feedback path with a selectable resistance. The bandwidth adjustable transimpedance amplifier is preferably implemented with a photodiode in a five pin package for an optical transceiver system, with a single pin providing a monitor out function and a rate select input.

Abstract: The present invention provides a method and system for managing, presenting and booking office space, conference rooms and other resources of a business center. Business center personnel may use the business center portal to manage the business center including managing the available business center facilities, generating reports, and generating work orders and work lists. Business center personnel may use the portal to create and change the details of business center facilities resources, equipment and services provided through the portal. Changes made to business center information at the portal are made in the business center's server, allowing the business center portal to be used to manage the business center's own servers and management system.

Abstract: The present invention provides a method and system for managing, presenting and booking office space, conference rooms and services of a business center. Visitors to a business center portal may view business center services, check the availability of business center services, and book the services that meet their needs. Business center personnel may use the business center portal to manage the business center including managing the available business service, generating reports, and generating work orders and work lists.

Abstract: The present invention provides a method and system for presenting and booking office space, conference rooms and other resources of a real estate center. Visitors to a real estate center portal may view real estate center properties, check the availability of real estate center facilities resources such as offices or conference rooms, and book the facilities that meet their needs. The present invention allows automatic updating of real estate center facilities resources and synchronization between a real estate center booking system and the management systems of real estate centers. Real estate centers that use the booking system to manage inventory of their real estate center can provide real time availability of their available resources through the real estate center portal.