Abstract: Various mechanisms and approaches identify multiple cells in an electronic design and multiple sets of stall prevention requirements or multiple sets of transactions for the multiple cells and determine dependencies between stall prevention requirements. A graph is constructed to represent the dependencies and the stall prevention requirements or the transactions involved in the dependencies by using the stall prevention requirements or the transactions as the nodes and the dependencies as the arcs connecting the nodes in the graph. One or more loop analyses are performed on the graph to identify one or more loops as one or more potential deadlocks. False deadlocks may be eliminated from further processing. The analyses and deadlock detection may be independently performed for each cell in sequence or in parallel to divide and conquer a complex electronic system design.

Abstract: An improved approach is provided to implement equivalency checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis. Instead, the two designs are checked to see if they are equivalent on the transaction-level. This approach abstracts the timing delays between the two designs, which allows verification of data transportation and transformation between the designs.