Patents by Inventor Lawrence D. Curley
Lawrence D. Curley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9563548Abstract: Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.Type: GrantFiled: August 11, 2015Date of Patent: February 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Glenn D. Gilda, Patrick J. Meaney
-
Patent number: 9459997Abstract: Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.Type: GrantFiled: May 1, 2014Date of Patent: October 4, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Glenn D. Gilda, Patrick J. Meaney
-
Patent number: 9437327Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.Type: GrantFiled: March 8, 2016Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
-
Publication number: 20160172055Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.Type: ApplicationFiled: March 8, 2016Publication date: June 16, 2016Inventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
-
Patent number: 9318171Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.Type: GrantFiled: September 30, 2014Date of Patent: April 19, 2016Assignee: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
-
Patent number: 9298614Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.Type: GrantFiled: March 14, 2014Date of Patent: March 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
-
Publication number: 20150347256Abstract: Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Lawrence D. Curley, Glenn D. Gilda, Patrick J. Meaney
-
Publication number: 20150318058Abstract: Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.Type: ApplicationFiled: May 1, 2014Publication date: November 5, 2015Applicant: International Business Machines CorporationInventors: Lawrence D. Curley, Glenn D. Gilda, Patrick J. Meaney
-
Patent number: 9142272Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.Type: GrantFiled: March 15, 2013Date of Patent: September 22, 2015Assignee: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
-
Publication number: 20150262706Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
-
Publication number: 20150019831Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
-
Publication number: 20140281326Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
-
Patent number: 8688880Abstract: Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.Type: GrantFiled: June 23, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Garrett M. Drapala, Michael A. Blake, Timothy C. Bronson, Lawrence D. Curley
-
Patent number: 8479070Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.Type: GrantFiled: June 24, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Ulrich Baur, Lawrence D. Curley, Ronald J. Frishmuth, Ralf Ludewig, Ching L. Tong, Tobias Webel
-
Patent number: 8364904Abstract: Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.Type: GrantFiled: June 21, 2010Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Michael A. Blake, Lawrence D. Curley, Garrett M. Drapala, Edward J. Kaminski, Craig R. Walters
-
Publication number: 20110320778Abstract: Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Garrett M. Drapala, Michael A. Blake, Timothy C. Bronson, Lawrence D. Curley
-
Publication number: 20110320898Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ulrich Baur, Lawrence D. Curley, Ronald J. Frishmuth, Ralf Ludewig, Ching L. Tong, Tobias Webel
-
Publication number: 20110314227Abstract: Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Lawrence D. Curley, Garrett M. Drapala, Edward J. Kaminski, JR., Craig R. Walters
-
Patent number: 7979732Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.Type: GrantFiled: July 3, 2007Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Lawrence D. Curley, John M. Isakson, Arjen Mets, Travis W. Pouarz, Thomas E. Rosser, Kristen M. Tucker
-
Publication number: 20090013206Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.Type: ApplicationFiled: July 3, 2007Publication date: January 8, 2009Inventors: Lawrence D. Curley, John M. Isakson, Arjen Mets, Travis W. Pouarz, Thomas E. Rosser, Kristen M. Tucker