Abstract: A multilevel analog recording and playback system is described. The analog recording and playback system provides a variety of analog processing functions to enhance system level integration. The analog recording and playback system is an fully configurable integrated device that includes a plurality of signal paths, a microphone automatic gain control (“AGC”) circuit, volume control and filtering circuit, speaker driver circuit, gain selectable analog input, auxiliary input and output paths, configurable summation amplifiers having mixing features, multilevel analog memory storage array, and user selectable programming duration.

Abstract: An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance element is connected in series in a mirrored configuration about the center impedance element.

Abstract: An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance elements is connected in series in a mirrored configuration about the center impedance element.

Abstract: An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance elements is connected in series in a mirrored configuration about the center impedance element.

Abstract: A multilevel analog recording and playback system is described. The analog recording and playback system provides a variety of analog processing functions to enhance system level integration. The analog recording and playback system is an fully configurable integrated device that includes a plurality of signal paths, a microphone automatic gain control (“AGC”) circuit, volume control and filtering circuit, speaker driver circuit, gain selectable analog input, auxiliary input and output paths, configurable summation amplifiers having mixing features, multilevel analog memory storage array, and user selectable programming duration.

Abstract: An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance elements is connected in series in a mirrored configuration about the center impedance element.

Abstract: Adaptive programming method and apparatus for flash memory analog storage. The present invention method is to adjust the voltage of the programming pulse each time based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse. The algorithm is “adaptive” because the voltage of each pulse is adapted to whatever the cell needs. If the cell is programming too slowly, the voltage is increased dramatically to make it faster. Conversely if the results show that a particular cell is programming too fast, the next voltage pulse is increased by only a small amount (or even decreased if necessary). Because the response of the cell is non-linear, a special analog circuit is used to calculate the optimum voltage for each pulse. As one alternative, a digital calculation may also be used to program the cells.

Abstract: The present invention is a charge pump circuit to reduce and distribute power supply current surges. The charge pump circuit includes a first clock line to provide a first clock thereon, a plurality of delay circuits connected in series, each delay circuit generating a delayed and inverted clock from its input clock on a respective output clock line, and a plurality of charge pump stages connected in series each to store charge thereon. The first clock line is coupled to the first charge pump stage and the plurality of output clock lines are coupled to a respective plurality of remaining charge pump stages. The operation of each charge pump stage is staggered to reduce and distribute the power supply current surges.

Abstract: The present invention relates to a method and apparatus for adjusting the gain of an amplifier circuit. A gain control circuit compares the output of the amplifier with a reference voltage and adjusts a variable resistor, thereby altering the gain of the amplifier.

Abstract: AC coupling and signal amplification using switched capacitors. The use of a switched capacitor to simulate a resistor in amplifier coupling in an integrated circuit processing audio frequency signals avoids the need for external components, reducing cost and eliminating the need for pinouts for the external components. In a system including an anti-aliasing filter, capacitive coupling is used for coupling between amplifiers, with the gain of the second amplifier being set by a feedback capacitor between the amplifier output and its input, as sized relative to the coupling capacitor. The switched capacitor in the feedback loop of the second amplifier preferably couples the output of the anti-aliasing filter back to the amplifier input, thereby minimizing the aliasing from the capacitor switching.

Abstract: The present invention is a method of indicating an end of message marker in a plurality of memory cells. The method includes the step of clearing a plurality of memory cells by programming the plurality of memory cells within a first predetermined voltage range to indicate an end of message. The method further includes the step of recording an input signal onto at least a portion of the plurality of memory cells within a second predetermined voltage range. The first and second predetermined voltage ranges are non-overlapping voltage ranges.

Abstract: An integrated circuit which operates to store an input analog signal within an analog storage device such as an EEPROM is disclosed. Initially, a target voltage is determined for applying to the memory cell with the target voltage set to about 90% of the input analog signal voltage. A high voltage ramp is applied to the memory cell to set the voltage of the memory cell to the target voltage. A read operation is simultaneously performed while the high voltage ramp is applied to detect the voltage stored on the cell and to terminate the application of the high voltage ramp once the target voltage is reached. Thereafter, a normal read operation is performed on the memory cell to detect the actual voltage of the cell. A new target voltage is determined based upon the actual voltage of the memory cell and the input analog signal voltage. The high voltage ramp is again connected to the memory cell to set the cell to the new target voltage while a simultaneous read operation is performed.

Abstract: A single chip, single or dual message multilevel analog signal recording and playback system is described. In one embodiment, the system comprises a record circuit, an analog storage array, a playback circuit, and a control circuit that independently controls signal storage segments and duration capability. The record circuit receives an audio signal and generates a filtered signal, which is stored in the analog storage array. The playback circuit is coupled to the storage array for retrieving the stored signal for playback. The system further includes a mixer circuit which receives an auxiliary signal and mixes the auxiliary signal with the stored signal during playback. The control circuit also features a novel audio, visual, and input/output functionality.

Abstract: An adaptive amplitude ramp controller that regulates how fast and how high a series of voltages is applied to a targeted non-volatile memory cell. The series of voltages include a coarse ramp pulse and at least one fine ramp pulse. The coarse ramp pulse undergoes a first ramp rate until a particular voltage is reached. Thereafter, it undergoes a second ramp rate until the cycle associated with the coarse ramp pulse is completed or a target voltage is reached. Programming of the non-volatile memory cell occurs during this portion of the course ramp pulse. Thereafter, the adaptive amplitude ramp controller produces at least one fine ramp pulse. The fine ramp pulse is quickly ramped up at a third ramp rate and then undergoes a fourth ramp rate until the final desired voltage of the non-voltage memory cell is generally reached.

Abstract: A circuit and method for adjusting the ramp voltage applied to a control gate of a non-volatile memory cell to improve programming accuracy. The method involves measuring an amount of additional voltage realized at a source of the floating gate transistor. Thereafter, a preset compensation ratio may be selected to reduce a ramp voltage applied to the control gate of the memory cell by an amount necessary to lessen the amount of additional voltage realized at the source of the floating gate transistor. This will reduce inaccurate measurement of voltages during the read-while-write voltage program technique. A voltage control circuit is connected to the control gate for precise reduction of the ramp voltage.

Abstract: The present invention discloses a circuit for controlling operation of a functional circuit in a device based on a test result during testing. The circuit comprises a first storage element configured to be in one of a first state and a second state according to the test result, and a first sensing element coupled to the first storage element for generating a first signal used to control the operation of the functional circuit.

Abstract: The present invention is an apparatus for storing a voltage level within a storage element such as an EEPROM. The apparatus includes a track and hold circuit that receives the voltage level to be stored and an integrator that determines a target voltage to be applied to the storage element representative of a voltage level less than the received voltage level. The apparatus further includes a voltage ramp circuit that applies a voltage ramp signal to the storage element for increasing an amount of voltage held in the storage element while simultaneously reading a voltage level of the storage element to determine whether the voltage of the storage element matches the target voltage and a comparator that deactivates the voltage ramp signal when the voltage of the storage element matches the target voltage.

Abstract: The present invention is an improvement in an analog storage device having a row of EEPROM cells. The improvement includes providing a reference EEPROM cell having first and second transistors connected in series, with a gate of the first transistor connected to a clear input line and a gate of the second transistor connected to a select input line. The improvement further includes providing a comparator having first and second inputs with the first input connected to a source of the second transistor and a second input connected to a reference voltage line and with an output of the comparator connected to the gate of the first transistor, wherein the gate of the first transistor is connected to gates of first transistors of each of the row of EEPROM cells.

Abstract: An integrated circuit which operates to store an input analog signal within an analog storage device such as an EEPROM is disclosed. Initially, a target voltage is determined for applying to the memory cell with the target voltage set to about 90% of the input analog signal voltage. A high voltage ramp is applied to the memory cell to set the voltage of the memory cell to the target voltage. A read operation is simultaneously performed while the high voltage ramp is applied to detect the voltage stored on the cell and to terminate the application of the high voltage ramp once the target voltage is reached. Thereafter, a normal read operation is performed on the memory cell to detect the actual voltage of the cell. A new target voltage is determined based upon the actual voltage of the memory cell and the input analog signal voltage. The high voltage ramp is again connected to the memory cell to set the cell to the new target voltage while a simultaneous read operation is performed.