Abstract: Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

Abstract: First signaling indicative of instructions to enter a self-refresh (SREF) mode can be received concurrently by a plurality of memory dies. Responsive to a memory die of the plurality of memory dies entering the SREF mode, self-refreshing of memory banks of the memory die can be delayed, at the memory die and based on fuse states of an array of fuses of the memory die, an amount of time relative to receipt of the signaling by the memory die. Delaying self-refreshing of memory banks of memory dies in a staggered, or asynchronous, manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

Abstract: First signaling indicative of instructions to enter a self-refresh (SREF) mode can be received concurrently by a plurality of memory dies. Responsive to a memory die of the plurality of memory dies entering the SREF mode, self-refreshing of memory banks of the memory die can be delayed, at the memory die and based on fuse states of an array of fuses of the memory die, an amount of time relative to receipt of the signaling by the memory die. Delaying self-refreshing of memory banks of memory dies in a staggered, or asynchronous, manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

Abstract: Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract: An I.D. collet has a housing with a hollow bore and an undercut portion; a taper screw slidable into and out of the hollow bore of the housing and having a conical head; a spindle having a hollow bore in alignment with the hollow bore of the housing for receiving the conical head of the taper screw into and out of the hollow bore of the spindle such that the conical head enlarges the diameter of the spindle; and a draw nut assembly threadably connected to the taper screw and having tangs abutting the undercut portion of the housing when the spindle reaches a preset location in the hollow bore of the spindle to prevent further enlargement of the spindle when the tangs come into contact with the undercut portion of the housing.

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract: A remote voltage regulator module (VRM) for high-current, low voltage applications. In one embodiment, an electronic system includes a VRM configured to provide a DC output voltage. The VRM is coupled to a load board via a first bus bar and a second bus bar. The VRM includes a first capacitance of a first amount, while the load board includes a second capacitance of a second amount. A loop between the VRM and the load board is formed by the first and second bus bars and first and second capacitances. The loop is characterized by a transfer function that is second order or less.

Abstract: A low inductance mount for decoupling capacitors. In one embodiment, a circuit carrier such as a printed circuit board (PCB) includes a surface layer, a first layer adjacent to the surface layer, and a second layer adjacent to the first layer. A conductive region is implemented on the surface layer, and is electrically coupled to a first circuit plane in the first layer. At least one mounting pad is located on the surface layer of the PCB within the conductive region. The mounting pad is electrically isolated from the remainder of the conductive region and is electrically coupled to a second circuit plane in the second layer. A capacitor is mounted on the PCB, wherein a first terminal of the capacitor is coupled to the conductive region and a second terminal is coupled to the mounting pad.

Abstract: Three vertical deflection windings of corresponding three deflection yokes that are mounted on three cathode ray tubes of a projection video are coupled in series through corresponding three connector pairs. Three horizontal deflection windings of the corresponding three deflection yokes are coupled in parallel through the corresponding three connector pairs. When any of the three connector pairs is left disengaged, a disabling signal that is indicative of a loss of a vertical deflection current in the series coupled vertical deflection windings is generated. The disabling signal is coupled to a corresponding video driver of each of the cathode ray tubes for providing beam current blanking to protect the screens of the tubes against a screen burn damage.