Abstract: In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Abstract: In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Abstract: A workstation controller is disclosed which operates in either full screen write mode or partial screen write mode. In one embodiment, the controller looks for a "Clear Display"(CD) command in the data stream from the host. If the data stream contains a CD command and if a screen image buffer is available, the controller operates in full screen write mode. Subsequent "Write to Device" (WTD) commands in the data stream are sent to the buffer, not to the device. When the controller detects the end of the data stream the entire contents of the buffer are sent to the display in one operation. If the controller does not detect a CD command in the data stream, or if the CD command is detected but a screen image buffer is not available, the controller operates in partial screen write mode. WTD commands in the data stream are sent directly to the display one at a time.

Abstract: In a processor having a real address space larger than its virtual address space, all of the physical memory is addressed by using a separate prefix register associated with each of the address registers to hold both a high-order address portion and a control bit specifying whether the address is to be translated or used as a direct real address.

Abstract: Multi-level indexed indirect addressing is provided with matched pairs of prefix bytes and suffix values which can surround any instruction. Each prefix code is distinguishable from an instruction code. Counters keep track of indirection levels.