Patents by Inventor Lawrence Douglas Andrews, Jr.

Lawrence Douglas Andrews, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160218088
    Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.
    Type: Application
    Filed: March 31, 2016
    Publication date: July 28, 2016
    Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, JR.
  • Patent number: 9305862
    Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: April 5, 2016
    Assignee: Invensas Corporation
    Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, Jr.
  • Patent number: 8742602
    Abstract: A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: June 3, 2014
    Assignee: Invensas Corporation
    Inventors: Terrence Caskey, Lawrence Douglas Andrews, Jr., Scott McGrath, Simon J. S. McElrea, Yong Du, Mark Scott
  • Patent number: 8723332
    Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: May 13, 2014
    Assignee: Invensas Corporation
    Inventors: Simon J. S. McElrea, Lawrence Douglas Andrews, Jr., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
  • Patent number: 8629543
    Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 14, 2014
    Assignee: Invensas Corporation
    Inventors: Simon J. S. McElrea, Lawrence Douglas Andrews, Jr., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
  • Publication number: 20130099392
    Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.
    Type: Application
    Filed: April 25, 2012
    Publication date: April 25, 2013
    Applicant: VERTICAL CIRCUITS, INC.
    Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, JR.
  • Patent number: 8324081
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: December 4, 2012
    Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
  • Patent number: 8178978
    Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: May 15, 2012
    Assignee: Vertical Circuits, Inc.
    Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, Jr.
  • Patent number: 8159053
    Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: April 17, 2012
    Assignee: Vertical Circuits, Inc.
    Inventors: Lawrence Douglas Andrews, Jr., Jeffrey S. Leal, Simon J. S. McElrea
  • Publication number: 20110147943
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Application
    Filed: March 4, 2011
    Publication date: June 23, 2011
    Applicant: Vertical Circuits, Inc.
    Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, JR., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
  • Patent number: 7923349
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: April 12, 2011
    Assignee: Vertical Circuits, Inc.
    Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
  • Publication number: 20110037159
    Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.
    Type: Application
    Filed: October 27, 2010
    Publication date: February 17, 2011
    Applicant: Vertical Circuits, Inc.
    Inventors: Simon J. S. McElrea, Lawrence Douglas Andrews, JR., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
  • Publication number: 20110012246
    Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.
    Type: Application
    Filed: September 28, 2010
    Publication date: January 20, 2011
    Applicant: Vertical Circuits, Inc.
    Inventors: Lawrence Douglas Andrews, JR., Jeffrey S. Leal, Simon J.S. McElrea
  • Patent number: 7843046
    Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: November 30, 2010
    Assignee: Vertical Circuits, Inc.
    Inventors: Lawrence Douglas Andrews, Jr., Jeffrey Leal, Simon J. S. McElrea
  • Publication number: 20090230528
    Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.
    Type: Application
    Filed: March 12, 2009
    Publication date: September 17, 2009
    Applicant: VERTICAL CIRCUITS, INC.
    Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, JR.
  • Publication number: 20090206458
    Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.
    Type: Application
    Filed: August 27, 2008
    Publication date: August 20, 2009
    Applicant: VERTICAL CIRCUITS, INC.
    Inventors: LAWRENCE DOUGLAS ANDREWS, JR., JEFFREY S. LEAL, SIMON J.S. McELREA
  • Publication number: 20090102038
    Abstract: A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die in the assembly and circuitry on a support; and interconnection between die in the stack can be made by way of connection of z-interconnects with bonds pads in the die attach side of the support near or at one or more die edges. Methods for preparing the die include processes carried out to an advanced stage at the wafer level or at the die array level.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 23, 2009
    Applicant: VERTICAL CIRCUITS, INC.
    Inventors: SIMON J.S. MCELREA, Marc E. Robinson, Lawrence Douglas Andrews, JR., Terrence Caskey, Scott McGrath, Yong Du, Al Vindasius
  • Publication number: 20090068790
    Abstract: Methods for depositing interconnect material at a target for electrical interconnection include pulsed dispense of the material. In some embodiments droplets of interconnect material are deposited in a projectile fashion. In some embodiments the droplets are shaped by movement of the deposition tool following a deposition pulse and prior to separation of the droplet mass from the tool.
    Type: Application
    Filed: May 20, 2008
    Publication date: March 12, 2009
    Applicant: Vertical Circuits, Inc.
    Inventors: Terrence Caskey, Lawrence Douglas Andrews, JR., Simon J.S. McElrea, Scott McGrath, Jeffrey S. Leal
  • Publication number: 20080315407
    Abstract: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 25, 2008
    Applicant: Vertical Circuits, Inc.
    Inventors: Lawrence Douglas Andrews, JR., Simon J.S. McElrea, Terrence Caskey, Scott McGrath, Yong Du
  • Publication number: 20080315434
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Applicant: Vertical Circuits, Inc.
    Inventors: Simon J.S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, JR., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu