Patents by Inventor Lawrence Douglas Andrews, Jr.
Lawrence Douglas Andrews, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160218088Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.Type: ApplicationFiled: March 31, 2016Publication date: July 28, 2016Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, JR.
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Patent number: 9305862Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.Type: GrantFiled: April 25, 2012Date of Patent: April 5, 2016Assignee: Invensas CorporationInventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, Jr.
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Patent number: 8742602Abstract: A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals.Type: GrantFiled: March 12, 2008Date of Patent: June 3, 2014Assignee: Invensas CorporationInventors: Terrence Caskey, Lawrence Douglas Andrews, Jr., Scott McGrath, Simon J. S. McElrea, Yong Du, Mark Scott
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Patent number: 8723332Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.Type: GrantFiled: May 20, 2008Date of Patent: May 13, 2014Assignee: Invensas CorporationInventors: Simon J. S. McElrea, Lawrence Douglas Andrews, Jr., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
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Patent number: 8629543Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.Type: GrantFiled: October 27, 2010Date of Patent: January 14, 2014Assignee: Invensas CorporationInventors: Simon J. S. McElrea, Lawrence Douglas Andrews, Jr., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
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Publication number: 20130099392Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.Type: ApplicationFiled: April 25, 2012Publication date: April 25, 2013Applicant: VERTICAL CIRCUITS, INC.Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, JR.
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Patent number: 8324081Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: GrantFiled: March 4, 2011Date of Patent: December 4, 2012Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
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Patent number: 8178978Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.Type: GrantFiled: March 12, 2009Date of Patent: May 15, 2012Assignee: Vertical Circuits, Inc.Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, Jr.
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Patent number: 8159053Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.Type: GrantFiled: September 28, 2010Date of Patent: April 17, 2012Assignee: Vertical Circuits, Inc.Inventors: Lawrence Douglas Andrews, Jr., Jeffrey S. Leal, Simon J. S. McElrea
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Publication number: 20110147943Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: ApplicationFiled: March 4, 2011Publication date: June 23, 2011Applicant: Vertical Circuits, Inc.Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, JR., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
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Patent number: 7923349Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: GrantFiled: June 19, 2008Date of Patent: April 12, 2011Assignee: Vertical Circuits, Inc.Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu
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Publication number: 20110037159Abstract: In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.Type: ApplicationFiled: October 27, 2010Publication date: February 17, 2011Applicant: Vertical Circuits, Inc.Inventors: Simon J. S. McElrea, Lawrence Douglas Andrews, JR., Scott McGrath, Terrence Caskey, Scott Jay Crane, Marc E. Robinson, Loreto Cantillep
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Publication number: 20110012246Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.Type: ApplicationFiled: September 28, 2010Publication date: January 20, 2011Applicant: Vertical Circuits, Inc.Inventors: Lawrence Douglas Andrews, JR., Jeffrey S. Leal, Simon J.S. McElrea
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Patent number: 7843046Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.Type: GrantFiled: August 27, 2008Date of Patent: November 30, 2010Assignee: Vertical Circuits, Inc.Inventors: Lawrence Douglas Andrews, Jr., Jeffrey Leal, Simon J. S. McElrea
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Publication number: 20090230528Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.Type: ApplicationFiled: March 12, 2009Publication date: September 17, 2009Applicant: VERTICAL CIRCUITS, INC.Inventors: Simon J. S. McElrea, Marc E. Robinson, Lawrence Douglas Andrews, JR.
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Publication number: 20090206458Abstract: A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.Type: ApplicationFiled: August 27, 2008Publication date: August 20, 2009Applicant: VERTICAL CIRCUITS, INC.Inventors: LAWRENCE DOUGLAS ANDREWS, JR., JEFFREY S. LEAL, SIMON J.S. McELREA
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Publication number: 20090102038Abstract: A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die in the assembly and circuitry on a support; and interconnection between die in the stack can be made by way of connection of z-interconnects with bonds pads in the die attach side of the support near or at one or more die edges. Methods for preparing the die include processes carried out to an advanced stage at the wafer level or at the die array level.Type: ApplicationFiled: October 15, 2008Publication date: April 23, 2009Applicant: VERTICAL CIRCUITS, INC.Inventors: SIMON J.S. MCELREA, Marc E. Robinson, Lawrence Douglas Andrews, JR., Terrence Caskey, Scott McGrath, Yong Du, Al Vindasius
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Publication number: 20090068790Abstract: Methods for depositing interconnect material at a target for electrical interconnection include pulsed dispense of the material. In some embodiments droplets of interconnect material are deposited in a projectile fashion. In some embodiments the droplets are shaped by movement of the deposition tool following a deposition pulse and prior to separation of the droplet mass from the tool.Type: ApplicationFiled: May 20, 2008Publication date: March 12, 2009Applicant: Vertical Circuits, Inc.Inventors: Terrence Caskey, Lawrence Douglas Andrews, JR., Simon J.S. McElrea, Scott McGrath, Jeffrey S. Leal
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Publication number: 20080315407Abstract: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g.Type: ApplicationFiled: June 20, 2008Publication date: December 25, 2008Applicant: Vertical Circuits, Inc.Inventors: Lawrence Douglas Andrews, JR., Simon J.S. McElrea, Terrence Caskey, Scott McGrath, Yong Du
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Publication number: 20080315434Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).Type: ApplicationFiled: June 19, 2008Publication date: December 25, 2008Applicant: Vertical Circuits, Inc.Inventors: Simon J.S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, JR., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu