Patents by Inventor Lawrence F. Wagner

Lawrence F. Wagner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7863691
    Abstract: Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and essentially symmetrical relative to an adjacent set. Arranging the sets in this manner allows adjacent diffusion regions of the same type (i.e., sources or drains) from adjacent sets to be merged. Merging of the diffusion regions provides several benefits, including but not limited to, reducing the device size, reducing the amount of required wiring for the device (i.e., reducing resistance) and reducing side capacitance between the now merged diffusion regions and the substrate. Also disclosed are embodiments of an associated design structure for the device and an associated method of forming the device.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Lawrence F. Wagner, Jr., Randy L. Wolf
  • Publication number: 20090224334
    Abstract: Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and essentially symmetrical relative to an adjacent set. Arranging the sets in this manner allows adjacent diffusion regions of the same type (i.e., sources or drains) from adjacent sets to be merged. Merging of the diffusion regions provides several benefits, including but not limited to, reducing the device size, reducing the amount of required wiring for the device (i.e., reducing resistance) and reducing side capacitance between the now merged diffusion regions and the substrate. Also disclosed are embodiments of an associated design structure for the device and an associated method of forming the device.
    Type: Application
    Filed: March 10, 2008
    Publication date: September 10, 2009
    Inventors: Lawrence F. Wagner, JR., Randy L. Wolf
  • Patent number: 7139990
    Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Yue Tan, Jean-Oliver Plouchart, Lawrence F. Wagner, Jr., Mohamed Talbi, John M. Safran, Kun Wu
  • Patent number: 6562666
    Abstract: Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device to substrate capacitance.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 13, 2003
    Assignee: International Business Machines Corporation
    Inventors: Heemyong Park, Fariborz Assaderaghi, Jack A. Mandelman, Ghavam G. Shahidi, Lawrence F. Wagner, Jr.
  • Patent number: 6490546
    Abstract: A process for obtaining accurate DC convergence in a DC phase of a circuit simulation program for models of field effect transistors (FETs) on a silicon-on-insulator (SOI) substrate. The process comprises running iterations of the DC phase of the circuit simulation program such that error criteria are satisfied, wherein the pseudo-time step changes at each iteration until it reaches a value such that a desired current value is achieved. DC convergence is also achieved by reducing the magnitude of the capacitive and/or charge elements connected to the floating body regions of the field effect transistors on the silicon-on-insulator substrate model during the DC phase to achieve a desired current value.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: December 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Richard Kimmel, Lawrence F. Wagner, Jr.
  • Patent number: 6141632
    Abstract: A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: October 31, 2000
    Assignee: International Business Machines Corporation
    Inventors: George E. Smith, III, Fariborz Assaderaghi, Paul D. Muench, Lawrence F. Wagner, Jr., Timothy L. Walters
  • Patent number: 6023577
    Abstract: A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that, current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: February 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: George E. Smith, III, Lawrence F. Wagner, Jr., Timothy L. Walters, Fariborz Assaderaghi
  • Patent number: 5446312
    Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.
    Type: Grant
    Filed: June 24, 1994
    Date of Patent: August 29, 1995
    Assignee: International Business Machines Corporation
    Inventors: Chang-Ming Hsieh, Louis L. G. Hsu, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr.
  • Patent number: 5371022
    Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: December 6, 1994
    Assignee: International Business Machines Corporation
    Inventors: Chang-Ming Hsieh, Louis L. G. Hsu, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr.
  • Patent number: 5341023
    Abstract: A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: August 23, 1994
    Assignee: International Business Machines Corporation
    Inventors: Chang-Ming Hsieh, Louis L. C. Hsu, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr.
  • Patent number: 5258640
    Abstract: An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: November 2, 1993
    Assignee: International Business Machines Corporation
    Inventors: Chang-Ming Hsieh, Louis L. Hsu, Phung T. Nguyen, Lawrence F. Wagner, Jr.
  • Patent number: 5109524
    Abstract: A digital processor has a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.
    Type: Grant
    Filed: October 28, 1988
    Date of Patent: April 28, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: Lawrence F. Wagner, Korbin S. Van Dyke, Wayne P. Burleson, Robert D. Hemming, John P. Guadagna
  • Patent number: 4862346
    Abstract: A digital processor has four components: a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.
    Type: Grant
    Filed: July 2, 1985
    Date of Patent: August 29, 1989
    Assignee: VLSI Technology, Inc.
    Inventors: Lawrence F. Wagner, Korbin S. Van Dyke, Wayne P. Burleson, Robert D. Hemming, John P. Guadagna
  • Patent number: 4857882
    Abstract: A comparator array logic (CAL) circuit has a plurality of interconnected comparators arranged in an array. Each of the comparators stores a digital value. The CAL circuit stores all of the digital values in a monotonically increasing or decreasing order. Each of the comparators receives the input data signal and compares the input data signal to the digital value stored in the comparator. A comparison signal is generated in response to the comparison. The comparison signal from each comparator is received by an end cell which also receives the comparison signal from the immediately adjacent comparator. The end cell generates an output signal. An end cell is associated with each comparator. The plurality of output signals from the end cells represent the location of the comparator which borders the value of the input data signal.
    Type: Grant
    Filed: September 14, 1988
    Date of Patent: August 15, 1989
    Assignee: VLSI Technology, Inc.
    Inventors: Lawrence F. Wagner, Wayne P. Burleson, John P. Guadagna
  • Patent number: 4852038
    Abstract: A calculating apparatus receives four operands ("a, b, c and d") simultaneously. A first multiplier/divider performs the calculation of a*b or a.div.b and provides an output u. A second multiplier/divider performs the calculation of c*d or c.div.d and provides an output v. An adder/subtractor receives u and v and performed the calculation of u+v and u-v. A controller controls the operation of the first and second multiplier/divider to select the operation of multiplication or division.
    Type: Grant
    Filed: July 2, 1985
    Date of Patent: July 25, 1989
    Assignee: VLSI Techology, Inc.
    Inventors: Lawrence F. Wagner, Wayne P. Burleson, Korbin S. Van Dyke
  • Patent number: 4626825
    Abstract: A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-zero bit of an integer, shifts the integer such that the leading non-zero bit is the leftmost bit. A look-up table receives the shifted integer and provides a number representative of the mantissa portion of the logarithm of the shifted number. An encoder receives a Point Set Input value, a scale value for said integer, and the number of binary positions shifted and generates the exponential portion of the logarithm of the integer. For converting logarithmic representation of a number into integer representation, the apparatus has a look-up table which receives the mantissa component of the logarithmic representation and provides a first number.
    Type: Grant
    Filed: July 2, 1985
    Date of Patent: December 2, 1986
    Assignee: VLSI Technology, Inc.
    Inventors: Wayne P. Burleson, Lawrence F. Wagner, Korbin S. Van Dyke
  • Patent number: 4415767
    Abstract: Speech signal analysis for data reduction, as stored for synthesis or recognition, is improved by features including: digital spectral analysis; reduction of channel data and bit allocation by selective summation of groups of contiguous data; using the mean average of the log amplitude to find the deviation for each channel; also using the instaneous shape of the mean value for each channel for pairs of adjacent frames, all combined to find a feature ensemble for each pair of adjacent frames.
    Type: Grant
    Filed: October 19, 1981
    Date of Patent: November 15, 1983
    Assignee: Votan
    Inventors: Stephen P. Gill, Lawrence F. Wagner, Gregory G. Frye, Klaus-Peter A. Bantowsky